MAX1112CAP-T Maxim Integrated, MAX1112CAP-T Datasheet - Page 3

• Manufacturer Part Number: MAX1112CAP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1112CAP-T

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 50 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V or External

ELECTRICAL CHARACTERISTICS (continued)
(V
(50ksps); 1µF capacitor at REFOUT; T
CONVERSION RATE
ANALOG INPUT
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REFIN
POWER REQUIREMENTS
Conversion Time (Note 4)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
Internal Clock Frequency
External Clock-Frequency Range
Input Voltage Range, Single-
Ended and Differential (Note 6)
Multiplexer Leakage Current
Input Capacitance
REFOUT Voltage
REFOUT Short-Circuit Current
REFOUT Temperature Coefficient
Load Regulation (Note 7)
Capacitive Bypass at REFOUT
Input Voltage Range
Input Current
Supply Voltage
Supply Current
Power-Supply Rejection
(Note 9)
DD
= 4.5V to 5.5V; unipolar input mode; V
PARAMETER
_______________________________________________________________________________________
SYMBOL
A
t
= T
CONV
t
PSR
V
ACQ
I
DD
DD
MIN
COM
+5V, Low-Power, Multi-Channel,
to T
= 0V; f
Internal clock
External clock, 500kHz, 10 clocks/conversion
External clock, 2MHz
(Note 5)
Used for data transfer only
Unipolar input, V
Bipolar input, V
On/off leakage current, V
0 to 0.5mA output load
(Note 8)
Full-scale input
C
Power-down
V
4.096V; full-scale input
MAX
DD
LOAD
= 4.5V to 5.5V; external reference,
; unless otherwise noted.)
SCLK
= 10pF
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
CONDITIONS
COM
COM
= V
= 0V
Operating mode
Reference disabled
Software
SHDN at DGND
REFIN
CH_
/2
= 0V or V
Serial 8-Bit ADCs
DD
3.936
MIN
4.5
20
50
1
0
1
1
±0.01
4.096
TYP
< 50
±0.4
400
±50
135
4.5
3.2
25
10
18
95
6
1
2
V
COM ±
V
REFIN
V
REFIN
4.256
DD
MAX
50
500
250
5.5
±1
±4
55
20
10
2
/2
+
ppm/°C
UNITS
MHz
kHz
kHz
mA
mV
mV
µA
µA
µA
µA
ps
pF
µF
µs
µs
ns
V
V
V
V
3