MAX1035EUP-T Maxim Integrated, MAX1035EUP-T Datasheet - Page 23

• Manufacturer Part Number: MAX1035EUP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1035EUP-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 115 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended/Differential
• Snr: 84.5 dB
• Interface Type: SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 879 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The MAX1034/MAX1035’s fastest maximum throughput
rate is achieved operating in external clock mode.
SCLK controls both the acquisition and conversion of
the analog signal, facilitating precise control over when
the analog signal is captured. The analog input sam-
pling instant is at the falling edge of the 14th SCLK
(Figure 2).
Since SCLK drives the conversion in external clock
mode, the SCLK frequency should remain constant
while the conversion is clocked. The minimum SCLK
frequency prevents droop in the internal sampling
capacitor voltages during conversion.
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1034/
MAX1035 will always be used in the external clock mode.
Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing
Table 7. Mode-Control Byte
BIT NUMBER
DOUT
SCLK
DIN
• User supplies one byte of SCLK, then drives CS
• After SSTRB transitions high, the user supplies
CS
7
6
5
4
3
2
1
0
high to relieve processor load while the ADC
converts
two bytes of SCLK and reads data at DOUT
IMPEDANCE
t
t
DV
CSS
HIGH
t
DS
START
1
BIT NAME
______________________________________________________________________________________
START
t
CL
M2
M1
M0
SEL2
1
0
0
0
8-/4-Channel, ±V
External Clock Mode (Mode 0)
ANALOG INPUT CONFIGURATION BYTE
SEL1
Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
Bit 3 must be a logic 1 for the mode-control byte.
Bit 2 must be a logic 0 for the mode-control byte.
Bit 1 must be a logic 0 for the mode-control byte.
Bit 0 must be a logic 0 for the mode-control byte.
SEL0
t
CP
DIF/SGL
t
CH
R2
R1
t
CSH
R0
t
t
8
DH
TR
IMPEDANCE
HIGH
The slowest maximum throughput rate is achieved with
the external acquisition method. SCLK controls the acqui-
sition of the analog signal in external acquisition mode,
facilitating precise control over when the analog signal is
captured. The internal clock controls the conversion of
the analog input voltage. The analog input sampling
instant is at the falling edge of the 16th SCLK (Figure 3).
Figure 16. DOUT and SSTRB Timing
REF
t
CSPW
START
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
DESCRIPTION
1
M2
SSTRB
Serial 14-Bit ADCs
Multirange Inputs,
DOUT
SCLK
CS
M1
MODE CONTROL BYTE
t
SSCS
External Acquisition Mode (Mode 1)
IMPEDANCE
M0
HIGH
t
CSS
1
t
DO
MSB
0
0
0
8
IMPEDANCE
HIGH
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