SPC5645SF1VLU Freescale Semiconductor, SPC5645SF1VLU Datasheet
SPC5645SF1VLU
Specifications of SPC5645SF1VLU
Available stocks
Related parts for SPC5645SF1VLU
SPC5645SF1VLU Summary of contents
Page 1
... DRAM controller allowing graphics RAM expansion externally. The MPC5645S is compatible with the existing development infrastructure of current Power Architecture devices and are supported with software drivers, operating systems and configuration code to assist with application development. © Freescale Semiconductor, Inc., 2009 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Block diagram ...
Page 2
... OPWM 8 ch, 16-bit ch, 16-bit OPWM / QDEC 16 channels, 10-bit 208 LQFP 416 TEPBGA e200z4d entry Yes Yes Yes Yes Yes Yes 6 motors Yes Yes Yes Yes Yes 20 channels, 10-bit Freescale Semiconductor ...
Page 3
... The 416-pin GPIO count does not include the DRAM interface, which is dedicated to DRAM only. 4 Nexus pins are multiplexed with other functional pins on 176 LQFP and 208 LQFP package options. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor MPC5645S 208 LQFP 176 LQFP 3 × ...
Page 4
... Reduced-Swing Differential Signal interface – Real Time Clock – Sound Generator Module – Stepper Motor Controller – Stepper Stall Detect – System Timer Module – Software Watchdog Timer – Timing Controller – Video Input Unit – Voltage regulator Freescale Semiconductor ...
Page 5
... Analog-to-Digital Converter (ADC) with a maximum conversion time of 1 s • — internal channels — external channels • Three Deserial Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous, communications with external devices • QuadSPI serial flash memory controller Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 5 ...
Page 6
... On-chip voltage regulator controller for regulating the 3.3–5 V supply voltage down to 1.2 V for core logic (requires external ballast transistor) 1 • Package: — 176 LQFP, 0.5 mm pitch outline Qorivva MPC5645S Microcontroller Data Sheet, Rev internal bus controllers with master/slave bus interface Freescale Semiconductor ...
Page 7
... PLL, flash memory, main regulator, etc.) at the cost of longer wake up latency. The system returns to RUN mode as soon as an event or interrupt is pending. Table 2 summarizes the operating modes of the MPC5645S. 1. See the device comparison table for package offerings for each device in the family. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 7 ...
Page 8
... LP 350 µs 4 µs 20 µ 200 µs — 30 µs LP 350 µs 8 µs 100 µ 200 µs Var 28 µs LP 200 µs 8 µs 100 µ 200 µs Var 28 µs — 500 µs 8 µs 100 µ 200 µs — Freescale Semiconductor — — 3 — 30 µs ...
Page 9
... ID of the last master to be granted access. The crossbar provides the following features: • Seven master ports: — e200z4d core instruction port — e200z4d core complex load/store data port — eDMA controller — DCU Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 9 ...
Page 10
... When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. Qorivva MPC5645S Microcontroller Data Sheet, Rev ADC, eMIOS, and General Freescale Semiconductor ...
Page 11
... Configurable digital input filter that can be applied general purpose input pins for noise elimination on external interrupts • Register configuration protected against change with soft lock for temporary guard or hard lock to prevent modification until next reset Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 11 ...
Page 12
... Optimized for burst transfers (read + write) — Programmable read prefetch capabilities 1.4.11 Memory Protection Unit (MPU) The MPU features the following: • Sixteen region descriptors for per master protection • Start and end address defined with 32-byte granularity Qorivva MPC5645S Microcontroller Data Sheet, Rev Freescale Semiconductor ...
Page 13
... TFT pads. The DCU3 features the following: • Display color depth bpp • Generation of all RGB and control signals for TFT • Four-plane blending Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 13 ...
Page 14
... The DCULite includes all features of the DCU3, including the PDI with the following exceptions: • Reduced from 4-plane to 2-plane blending • Reduced from 16 layers to 4 layers • Reduced CLUT size Qorivva MPC5645S Microcontroller Data Sheet, Rev Freescale Semiconductor ...
Page 15
... Supports 16-wide and 32-wide DDR1, DDR2, and LPDDR1 DRAM devices • Controller supports one chip select, 8-bank DRAM system • Supports dynamic on-die termination in the host device and in the DRAM • Supports memory sizes as small as 64 Mbit Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 15 ...
Page 16
... Programmable pulse period and duty cycle — Supports 0% and 100% duty cycle — Shared or independent time bases • Programmable phase shift between channels • 4 channels of Quadrature Decode • DMA transfer support Qorivva MPC5645S Microcontroller Data Sheet, Rev Freescale Semiconductor ...
Page 17
... The DSPI features: • Full duplex, synchronous transfers • Master or slave operation • Programmable master bit rates • Programmable clock polarity and phase • End-of-transmission interrupt flag • Programmable transfer baud rate Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 17 ...
Page 18
... The modules are LIN state machine compliant to the LIN 1.3, 2.0, and 2.1 Specifications and handle LIN frame transmission and reception without CPU intervention. Other features include: • Autonomous LIN frame handling • Message buffer to store identifier and up to eight data bytes • Supports message length bytes Qorivva MPC5645S Microcontroller Data Sheet, Rev Freescale Semiconductor ...
Page 19
... Repeated START signal generation • Acknowledge bit generation/detection • Bus-busy detection 1.4.26 System clocks and clock generation modules The system clock on the MPC5645S can be derived from an external oscillator, an on-chip FMPLL, or the internal 16 MHz oscillator. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 2 C) controller modules 19 ...
Page 20
... The Real Timer Counter supports wake-up from Low Power modes or Real Time Clock generation • Configurable resolution for different timeout periods — resolution for >1 hour period — resolution for 2 second period Qorivva MPC5645S Microcontroller Data Sheet, Rev Freescale Semiconductor ...
Page 21
... The SSD module features the following: • Programmable full step state • Programmable integration polarity • Blanking (recirculation) state • 16-bit integration accumulator register Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 21 ...
Page 22
... Run-time access to embedded processor memory map via the JTAG port. This allows for enhanced download/upload capabilities. • Watchpoint Messaging via the auxiliary pins provides visibility when debugging. • Watchpoint Trigger enablement of Program and/or Data Trace Messaging enhances debug capability. Qorivva MPC5645S Microcontroller Data Sheet, Rev Freescale Semiconductor ...
Page 23
... Auxiliary interface for higher data input/output. • Registers for Program Trace, Data Trace, Ownership Trace, and Watchpoint Trigger. • All features are controllable and configurable via the JTAG port. • Nexus Auxiliary port is supported on the 416BGA package. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 23 ...
Page 24
... PD8 / M2C0M / SSD2_0 99 PD7 / M1C1P / SSD1_3 PD6 / M1C1M / SSD1_2 / eMIOS0[23] 98 PD5 / M1C0P / SSD1_1 / eMIOS0[16 PD4 / M1C0M / SSD1_0 / eMIOS0[8] 95 VSSM VDDM 94 PD3 / M0C1P / SSD0_3 / eMIOS0[ PD2 / M0C1M / SSD0_2 / eMIOS1[23] 91 PD1 / M0C0P / SSD0_1 / eMIOS1[16] PD0 / M0C0M / SSD0_0 / eMIOS1[8] 90 VDDE_B 89 Freescale Semiconductor ...
Page 25
... VSS 47 VDDE_B 48 TCK / PH0 49 TDI / PH1 50 TDO / PH2 51 TMS / PH3 52 Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor MPC5645S 208 LQFP Top view Figure 3. 208-pin LQFP pinout 156 VDDE_B 155 PA13 / DCU_G5 / RSDS6M 154 PA12 / DCU_G4 / RSDS6P 153 PA11 / DCU_G3 / RSDS5M ...
Page 26
TEPBGA package pinout Figure 4 shows the pinout for the 416 TEPBGA package ddr_dq[2 ddr_dq[2 ddr_dq[2 ddr_dq[2 A 30] 31] ddr_ba[0]ddr_ba[1]ddr_ba[ ddr_dq[2 ddr_dqs[ ddr_dm[3 B VSS ...
Page 27
... MHz) external oscillator pads (EXTAL, XTAL) are tristate. • The following pads are pull-up: — PB[6] — PH[0] — PH[1] — PH[3] 2.4.2 Voltage supply pins Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 27 ...
Page 28
... M12,M13,M14,M15, M17,M3,N10,N12,N 13,N14,N15,N16,P 11,P12,P13,P14,P1 5,P17,P2,P25,R10, R12,R13,R14,R15, R16,R3,T11,T13,T1 5,T17,U10,U12,U14 ,U16,V2,Y1 24 — 6, 19, 37, 48, 56, 63, AD13,AD19,AD2,A 77, 105, 138, 146, D7,AE10,AE16,AE4 156, 164, 184, 198 ,B17,B21,B24,C19, E25,H24,L25,N24 AC22 96 AD22 20 AA4 21 — 93 AD23 94 AC23 Freescale Semiconductor ...
Page 29
... Analog input of the 32KHz oscillator amplifier circuit. XTAL32 Analog output of the 32 KHz oscillator amplifier circuit. Input for the clock generator in bypass mode. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 176 LQFP 94, 104 95, 105 25 22 — — Table 4. System pin descriptions ...
Page 30
... AC7 29 29 AA3 — 145, 165 J24,D24 26 26 AA2 1 Pin number 208 LQFP 416 TEPBGA 201 A17 189 C20 206 B18 190 B20 191 A20 202 D16 203 C16 204 B16 205 A16 n/a AD8 n/a AE8 n/a AC17 n/a AD9 n/a AD17 n/a AC20 Freescale Semiconductor ...
Page 31
... DRAM Data Bus [24] DDR_DQ[23] DRAM Data Bus [23] DDR_DQ[22] DRAM Data Bus [22] DDR_DQ[21] DRAM Data Bus [21] DDR_DQ[20] DRAM Data Bus [20] DDR_DQ[19] DRAM Data Bus [19] Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 5. Nexus pins (continued) Pad PCR type 176 LQFP M PCR[186] n/a M PCR[187] n/a ...
Page 32
... PCR[229] None, None Output DDR PCR[236] Output DDR PCR[235] Output DDR PCR[234] Output DDR PCR[233] Pin number RESET 2 config 416 TEPBGA Output, B4 None Output, G3 None Output, K3 None Output, P3 None Freescale Semiconductor ...
Page 33
... DRAM address [1] DDR_A[0] DRAM address [0] DRAM Bank Address DDR_BA[2] DRAM Bank Address[2] DDR_BA[1] DRAM Bank Address[1] DDR_BA[0] DRAM Bank Address[0] DRAM Control Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor I/O Pad PCR direction type Output DDR PCR[217] Output DDR PCR[216] Output ...
Page 34
... PCR[225] Output DDR NA Output DDR PCR[222] Output DDR PCR[223] Input — NA Input — NA Pin number RESET 2 config 416 TEPBGA Output, B6 None Output, B7 None Output, B9 None Output, D5 Pull Down Output, C7 None Output, D7 None Output, D8 Pull Down Output, D9 None — J4 — F2,J2,M2,R2 Freescale Semiconductor ...
Page 35
... For PG[11], the PCR[282] OBE bit is fully controlled by the TCON module and will become an output whenever the DCU3 alternate option is selected. Therefore, only select the DCU3 function on this pin when ready to configure clock for a TFT panel. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor VIU[9:0] VIU2 RGB565 ...
Page 36
Functional ports The functional port pins are listed in Table 7. Port Alternate PCR Function 1 pin function PORT A PA[0] PCR[0] Option 0 GPIO[0] Option 1 DCU_R0 Option 2 SDA_1 Option 3 eMIOS0[18] PA[1] PCR[1] Option 0 GPIO[1] ...
Page 37
Port Alternate PCR Function 1 pin function PA[8] PCR[8] Option 0 GPIO[8] Option 1 DCU_G0 Option 2 SCL_2 Option 3 eMIOS0[20] PA[9] PCR[9] Option 0 GPIO[9] Option 1 DCU_G1 Option 2 SDA_2 Option 3 eMIOS0[19] PA[10] PCR[10] Option 0 GPIO[10] ...
Page 38
Port Alternate PCR Function 1 pin function PB[1] PCR[17] Option 0 GPIO[17] Option 1 CANRX_0 Option 2 RXD_0 Option 3 — PB[2] PCR[18] Option 0 GPIO[18] Option 1 TXD_0 Option 2 — Option 3 — PB[3] PCR[19] Option 0 GPIO[19] ...
Page 39
Port Alternate PCR Function 1 pin function PB[10] PCR[26] Option 0 GPIO[26] Option 1 CANRX_1 Option 2 I2S_DO/PWMO Option 3 — PB[11] PCR[27] Option 0 GPIO[27] Option 1 CANTX_1 Option 2 SGM_MCLK Option 3 — PB[12] PCR[28] Option 0 GPIO[28] ...
Page 40
Port Alternate PCR Function 1 pin function PC[4] PCR[34] Option 0 GPIO[34] Option 1 — Option 2 — Option 3 — PC[5] PCR[35] Option 0 GPIO[35] Option 1 — Option 2 — Option 3 — PC[6] PCR[36] Option 0 GPIO[36] ...
Page 41
Port Alternate PCR Function 1 pin function PC[13] PCR[43] Option 0 GPIO[43] Option 1 — Option 2 MA2 Option 3 CS0_1 PC[14] PCR[44] Option 0 GPIO[44] Option 1 — Option 2 — Option 3 — PC[15] PCR[45] Option 0 GPIO[45] ...
Page 42
Port Alternate PCR Function 1 pin function PD[6] PCR[52] Option 0 GPIO[52] Option 1 M1C1M Option 2 SSD1_2 Option 3 eMIOS0[23] PD[7] PCR[53] Option 0 GPIO[53] Option 1 M1C1P Option 2 SSD1_3 Option 3 — PD[8] PCR[54] Option 0 GPIO[54] ...
Page 43
Port Alternate PCR Function 1 pin function PD[15] PCR[61] Option 0 GPIO[61] Option 1 M3C1P Option 2 SSD3_3 Option 3 eMIOS0[15] PORT E PE[0] PCR[62] Option 0 GPIO[62] Option 1 M4C0M Option 2 SSD4_0 Option 3 — PE[1] PCR[63] Option ...
Page 44
Port Alternate PCR Function 1 pin function PORT F PF[0] PCR[70] Option 0 GPIO[70] Option 1 eMIOS1[19] Option 2 EVTO Option 3 DCULITE_B2 PF[1] PCR[71] Option 0 GPIO[71] Option 1 eMIOS1[20] Option 2 MSEO Option 3 DCULITE_B3 PF[2] PCR[72] Option ...
Page 45
Port Alternate PCR Function 1 pin function PF[9] PCR[79] Option 0 GPIO[79] Option 1 SCL_0 Option 2 CS1_1 Option 3 TXD_1 PF[10] PCR[80] Option 0 GPIO[80] Option 1 QUADSPI_PCS_A Option 2 — Option 3 EVTI PF[11] PCR[81] Option 0 GPIO[81] ...
Page 46
Port Alternate PCR Function 1 pin function PG[2] PCR[88] Option 0 GPIO[88] Option 1 DCU_B2 Option 2 — Option 3 — PG[3] PCR[89] Option 0 GPIO[89] Option 1 DCU_B3 Option 2 — Option 3 — PG[4] PCR[90] Option 0 GPIO[90] ...
Page 47
Port Alternate PCR Function 1 pin function PG[11] PCR[97] Option 0 GPIO[97] Option 1 DCU_PCLK Option 2 — Option 3 — PG[12] PCR[98] Option 0 GPIO[98] Option 1 CS0_1 Option 2 PDI_DE Option 3 DCULITE_B7 PG[13] — — Reserved PG[14] ...
Page 48
Port Alternate PCR Function 1 pin function PH[6] — — Reserved PH[7] — — Reserved PH[8] — — Reserved PH[9] — — Reserved PH[10] — — Reserved PH[11] — — Reserved PH[12] — — Reserved PH[13] — — Reserved PH[14] ...
Page 49
Port Alternate PCR Function 1 pin function PJ[5] PCR[110] Option 0 GPIO[110] Option 1 VIU3_PDI1 Option 2 eMIOS0[20] Option 3 eMIOS0[16] PJ[6] PCR[111] Option 0 GPIO[111] Option 1 VIU4_PDI2 Option 2 eMIOS0[19] Option 3 eMIOS0[15] PJ[7] PCR[112] Option 0 GPIO[112] ...
Page 50
Port Alternate PCR Function 1 pin function PJ[14] PCR[119] Option 0 GPIO[119] Option 1 QUADSPI_CLK_B Option 2 eMIOS1[17] Option 3 PDI_PCLK PJ[15] PCR[120] Option 0 GPIO[120] Option 1 QUADSPI_IO3_B Option 2 eMIOS1[9] Option 3 VIU6_PDI14 PORT K PK[0] PCR[121] Option ...
Page 51
Port Alternate PCR Function 1 pin function PK[7] PCR[128] Option 0 GPIO[128] Option 1 RXD_2 Option 2 DCULITE_R2 Option 3 TCON[8] PK[8] PCR[129] Option 0 GPIO[129] Option 1 TXD_2 Option 2 DCULITE_R3 Option 3 TCON[9] PK[9] PCR[130] Option 0 GPIO[130] ...
Page 52
Port Alternate PCR Function 1 pin function PL[2] PCR[135] Option 0 GPIO[135] Option 1 — Option 2 CANRX_0 Option 3 eMIOS1[22] PL[3] PCR[136] Option 0 GPIO[136] Option 1 — Option 2 CANTX_0 Option 3 eMIOS1[23] PL[4] PCR[137] Option 0 GPIO[137] ...
Page 53
Port Alternate PCR Function 1 pin function PL[11] PCR[144] Option 0 GPIO[144] Option 1 eMIOS1[11] Option 2 DCULITE_G3 Option 3 — PL[12] PCR[145] Option 0 GPIO[145] Option 1 eMIOS1[12] Option 2 DCULITE_G4 Option 3 — PL[13] PCR[146] Option 0 GPIO[146] ...
Page 54
Port Alternate PCR Function 1 pin function PM[5] PCR[152] Option 0 GPIO[152] Option 1 VIU5_PDI13 Option 2 eMIOS1[22] Option 3 DCU_TAG PM[6] PCR[153] Option 0 GPIO[153] Option 1 VIU6_PDI14 Option 2 eMIOS1[23] Option 3 DCULITE_TAG PM[7] PCR[154] Option 0 GPIO[154] ...
Page 55
Port Alternate PCR Function 1 pin function PM[15] — — Reserved PORT N PN[0] PCR[161] Option 0 GPIO[161] Option 1 DCULITE_HSYNC Option 2 — Option 3 TCON[4] PN[1] PCR[162] Option 0 GPIO[162] Option 1 DCULITE_VSYNC Option 2 — Option 3 ...
Page 56
Port Alternate PCR Function 1 pin function PN[8] PCR[169] Option 0 GPIO[169] Option 1 DCULITE_R6 Option 2 — Option 3 TCON[10] PN[9] PCR[170] Option 0 GPIO[170] Option 1 DCULITE_R7 Option 2 — Option 3 TCON[11] PN[10] PCR[171] Option 0 GPIO[171] ...
Page 57
Port Alternate PCR Function 1 pin function PP[1] PCR[178] Option 0 GPIO[178] Option 1 DCULITE_G7 Option 2 — Option 3 eMIOS0[22] PP[2] PCR[179] Option 0 GPIO[179] Option 1 DCULITE_B0 Option 2 CANRX_2 Option 3 VIU4_PDI12 PP[3] PCR[180] Option 0 GPIO[180] ...
Page 58
Port Alternate PCR Function 1 pin function PP[12] — — Reserved PP[13] — — Reserved PP[14] — — Reserved PP[15] — — Reserved 1 Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIUL module. ...
Page 59
... Qorivva MPC5645S Microcontroller Data Sheet, Rev Table 9. Pad Types Function Slow (pad_ssr, pad_ssr_hv) Medium (pad_msr, pad_msr_hv) Fast (pad_fc) Input/output with analog features (pad_tgate, pad_tgate_hv) Input only with analog features (pad_ae, pad_ae_hv) Stepper Motor Detector DDR pads RSDS pads Freescale Semiconductor ...
Page 60
... In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column. Qorivva MPC5645S Microcontroller Data Sheet, Rev NOTE This could be done by SS Freescale Semiconductor ...
Page 61
... D Voltage on VDDE_A (I/O supply) pin with DDE_A respect to ground ( Voltage on VDDE_B (I/O supply) pin with DDE_B respect to ground (V Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 10 Table 10. Parameter Classifications Tag description NOTE Table 11. Absolute maximum ratings Parameter Conditions — ) SSA Relative to V — ...
Page 62
... and V DDE_A DDE_B , V SSE_A > must not exceed the SS Value Unit Min Max +3.0 +3 –0 –0 1.08 1.32 V Freescale Semiconductor SpecID D1.10 D1.11 D1.12 D1.13 — D1.15 D1.16 D1.17 D1.18 , DDM , and SSPLL SpecID D2.1 D2.2 D2.3 ...
Page 63
... When voltage drops below V LVDHVL 8 V refers collectively to I/O voltage supply grounds, i.e should not be less than V DDE_A DDA 10 Guaranteed by device validation. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Conditions — ) SSR Relative to V — — — — DDE_A ...
Page 64
... V –0 –0 1.08 1.32 V +3.0 +3 +3.0 +3.6 V –0 –0 1.08 1 –0 DDmin DDmax +4.5 +5.5 V +3.0 +3.6 V +4.5 +5.5 V +1.62 +3.6 V +1.62 +3.6 V +3.0 +3.6 V — 12 V/ms D2.34 –40 +105 °C –40 +105 –40 +140 — Freescale Semiconductor Spe- cID D2.19 D2.20 D2.21 D2.22 D2.23 D2.24 D2.25 D2.26 D2.27 D2.28 D2.29 D2.30 D2.31 D2.32 D2.33 D2.35 D2.36 ...
Page 65
... D Junction to Ambient Natural Convection Junction to Ambient JMA Junction to Ambient JMA Junction to Board Junction to Case (Top) JCtop Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor , DDE_A DDE_B DD_DR /V pair SSE_A SSE_B SSE_A . Parameter Conditions 2 ...
Page 66
... Four layer board - 2s2p can be obtained from the equation C/W) 1 (continued) Value Unit SpecID — 2 °C/W D3.14 1 Value Unit SpecID 26 °C/W D3.15 18 °C/W D3.16 20 °C/W D3.17 15 °C/W D3.18 — 10 °C/W D3.19 — 6 °C/W D3.20 — 2 °C/W D3.21 Eqn. 1 Freescale Semiconductor ...
Page 67
... This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 68
... Mountain View, CA 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. Qorivva MPC5645S Microcontroller Data Sheet, Rev ( C/W) Eqn. 4 Freescale Semiconductor ...
Page 69
... Additionally, 10 F should be placed between the DDPLL SSPLL DDR Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 17. EMI testing specifications Conditions Clocks FOSC – 8MHz, External Crystal FCPU – 124MHz FBUS – 124MHz No PLL Frequency ...
Page 70
... Cload = 10 µ Conditions Min Max Unit SpecID 3.0 5.5 V — -40 140 °C — — — 450 mA — 1.330 V 1.145 1.32 1.145 — µF 0.05 0.2 0.2 1 — — –30 dB –100 –30 –30 — 10 (max 100 ns — 500 µs Freescale Semiconductor D5.1 D5.2 D5.3 D5.4 D5.5 D5.6 D5.7 D5.8 D5.9 D5.10 ...
Page 71
... LVDHV5 monitors V when application uses device in the 5.0V ± 10% range DD • LVDLVCOR monitors power domain No. 1 • LVDLVBKP monitors power domain No. 0 Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Parameter Conditions Reference included °C No load @ Full load DC load current Pre-trimming sigma < ...
Page 72
... C — 17 105 C — –40 C — 645 — 1100 — 1531 — 3 — 9 105 C — 17.67 A Freescale Semiconductor SpecID D5.11 D5.12 D5.13 D5.14 D5.15 D5.16 D5.17 2 Unit Max 3 375 mA — mA — 23.5 mA 45.5 A — — 5500 — mA — 36.5 ...
Page 73
... GPU accessing internal SRAM and external DRAM, DMA, RLE, and VIU active, Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/ADC/SMD/SSD/SGM) and running at max frequency, periodic SW/WDG timer reset enabled. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 1 Conditions SXOSC (32KHz) ON and RTC ...
Page 74
... With hysteresis disabled — With hysteresis enabled 0.65Vdd33 With hysteresis enabled — Weak pull inactive Value Unit SpecID Min Max 1.08 1.47 V 3.0 3.6 V 3.0 3.6 V 0.65Vdde Vdde+0.3 V 0.55Vdde Vdde+0.3 Vss–0.3 0.35Vdde V Vss–0.3 0.40Vdde 0.1Vdde — V Vdd33+0.3 V Vss–0.3 0.35Vdd33 V A 25 150 A –2.5 2.5 Freescale Semiconductor D9.1 D9.2 D9.3 D9.4 D9.5 D9.6 D9.7 D9.8 D9.9 D9.10 ...
Page 75
... Ioh is defined as the current sourced by the pad to drive the output to Voh. 2 Iol is defined as the current sunk by the pad to drive the output to Vol. Pad C pad_fc D pad_msr pad_ssr Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Condition Weak pull inactive Refer to Table 24 Refer to Table 24 Iol_fod_h = 10 mA Drive mode Minimum Ioh (mA ...
Page 76
... Value Unit SpecID Min Max 1.08 1.32 V 4.5 5.5 V 3.0 3.6 V 0.65Vdde Vdde+0.3 V Vss–0.3 0.35Vdde V 0.55Vdde Vdde+0.3 V Vss–0.3 0.40Vdde V 0.1Vdde — V A 35 135 A 35 200 A –2.5 2.5 –150 150 nA 0.8Vdde — V — 0.2Vdde V 2.64 — V 11.6 40.7 mA 17.7 68.2 mA 6.0 21.3 mA 9.2 36.3 mA 250 800 Freescale Semiconductor D9.17 D9.18 D9.19 D9.20 D9.21 D9.22 D9.23 D9.24 D9.25 D9.26 D9.27 D9.28 D9.29 D9.30 D9.31 D9.32 D9.33 D9.34 D9.35 D9.39 ...
Page 77
... SR Pad_tgate_hv input resistance Pad pad_msr_hv 0.818 nA pad ssr_hv 0.818 nA pad_i_hv 0.307 nA biasref_hv Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 27. DC electrical specifications Condition — — — With hysteresis enabled With hysteresis enabled With hysteresis disabled With hysteresis disabled — ...
Page 78
... Drive/slew select IDDE (mA Freescale Semiconductor Max 0 — — — — — — — — — — — — — — — — — ...
Page 79
... SR Input low voltage Voh SR Output high voltage Vol SR Output low voltage Table 31. Output drive current @ VDDE = 3.3 V (+/-10%) Pad C pad_st_acc D pad_st_dq D pad_st_clk D pad_st D pad_st_odt D pad_st_ck D Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 1 Load (pF) VDDE (V) 50 5.5 50 5.5 50 5.5 200 5.5 Value Parameter Min 1.08 3.0 3.0 1.3 Vref–0.05 Vref+0.20 — ...
Page 80
... Qorivva MPC5645S Microcontroller Data Sheet, Rev Value Parameter Min 1.08 2.3 3.0 0.49Vdde Vref–0.04 Vref+0.15 — Vtt+0.81 — Minimum Ioh (mA) Minimum Iol (mA) –16.2 –16.2 –16.2 Unit SpecID Max 1.47 V D9.80 2.7 V D9.81 3.6 V D9.82 0.51Vdde V D9.83 Vref+0.04 V D9.84 — V D9.85 Vref–0.15 V D9.86 — V D9.87 Vtt–0.81 V D9.88 Libraries 16.2 6MDDR 16.2 6MDDR 16.2 6MDDR Freescale Semiconductor ...
Page 81
... Output high voltage Vol SR P Output low voltage Table 35. Output drive current @ VDDE = 1.8 V (+/-100mV) Pad Drive mode pad_st_acc D pad_st_dq D pad_st_clk D Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Parameter Min 1.08 1.7 3.0 0.49Vdde Vref–0.04 Vref+0.125 — Vtt+0.81 — Minimum Ioh (mA) 000 –3.57 001 – ...
Page 82
... Min Rainbow supports only 150 120 ohm termination and that can be enabled by enabling any bit of the termination control register (all of them are OR’ed). Vtrip max (V) 0.79 0.56 0.65 0.33 1.40 Value Unit SpecID Typ Max 150 180 D9.98 Vtrip min Hysteresis min (V) 0.44 0.07 0 0.3 0.16 0 0.3 — Freescale Semiconductor ...
Page 83
... V RESET filtered by filtered by lowpass filter hysteresis W Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Figure 7. Startup reset requirements unknown reset filtered by state lowpass filter W FRST FRST W NFRST Figure 8. Noise filtering on reset signal hw_rst ‘ ‘ ...
Page 84
... V +0 -0.4 — 0.35V V DD 0.1V — — — — 0. — — 0.1V DD — — 0.5 — — — — 20 — — 40 — — 12 — — 25 — — 40 — — 400 — — — — µA Freescale Semiconductor D8.1 D8.2 D8.3 D8.4 D8.5 D8.6 D8.7 D8.8 ...
Page 85
... V C EXTAL pin oscillation amplitude PP,EXTAL MHz pF. OSC 2 Maximum value is for extreme cases using high Q, low frequency crystals. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor < 5pF). PKG Conditions Min Loop controlled Pierce 4.0 — 100 Loop controlled Pierce — ...
Page 86
... Figure 9. Crystal oscillator and resonator connection scheme PC[14]/PC[15] must not be directly used to drive external circuits DDMIN V XTAL V XOSCLP Figure 10. Slow external crystal oscillator electrical characteristics Qorivva MPC5645S Microcontroller Data Sheet, Rev DEVICE NOTE 90% 10% T valid internal clock XOSCLPSU PC[15] PC[14] 1/f XOSCLP Freescale Semiconductor ...
Page 87
... All values need to be confirmed during device validation. 3 PLLIN clock retrieved directly from XOSCHS clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify f Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 1 Conditions Min — ...
Page 88
... Min Typ Max — 16 — MHz O12.1 — — 200 µA — — 10 µA — –5 — Value 1 Unit SpecID Min Typ Max — 128 — kHz — — 5 µA –10 — +10 % Freescale Semiconductor O12.2 O12.3 O12.5 O13.1 O13.2 O13.4 ...
Page 89
... Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. 4.16 ADC parameters The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 44. Program and erase specifications Min Value 4 — ...
Page 90
... The ideal transfer curve (5) (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (4) (5) Center of a step of the actual transfer curve (3) 1 LSB (ideal 1017 1018 1019 1020 1021 1022 1023 V (LSB ) in(A) ideal Gain Error GE 1 LSB ideal = V / 1024 DDA Freescale Semiconductor ...
Page 91
... R Sampling Switch Impedance AD C Pin Capacitance (two contributions Sampling Capacitance S Figure 12. Input Equivalent Circuit (Precise Channels) Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor equal to 3 pF, a resistance of 330k is obtained ( and the sum ...
Page 92
... and R ) SW2 , Figure 12): A charge sharing phenomenon < << and C to the sampling capacitance the two capacitances C and Freescale Semiconductor and C are P2 occurs ( are in series, ...
Page 93
... The two transients above are not influenced by the voltage source that, due to the presence of the R provide the extra charge to compensate the voltage drop on C the filter is very high with respect to the sampling time (T Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 1 ...
Page 94
... A value: F 2048 C S (Conversion Rate vs. Filter Pole) = conversion Rate longer than the sampling time definitively much higher than the F F Equation 12 between the ideal and real sampled C S Freescale Semiconductor ), Eqn. 12 Eqn. 13 ...
Page 95
... INJ 5 INL CC P Integral Non Linearity 5 DNL CC P Differential Non Linearity 5 OFS CC T Offset error 5 GNE CC T Gain error Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 46. ADC electrical characteristics 1 Conditions — — — — — MHz, ...
Page 96
... LSB — — — LSB . After the end of the sample time ADC_S ADC_S Drive/slew Drive load rate select (pF) Max MSB, LSB 2 200 200 200 210 / 210 50 220 / 220 200 Freescale Semiconductor D15.22 D15.23 depend ...
Page 97
... Can be used on the tester. 4.17.2 AC specification for CMOS090LP2fg library @ VDDE = 5.0 V Table 48. Functional pad type AC specifications Name C 2 pad_msr_hv C 4 Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Prop. delay (ns) Rise/fall edge (ns) 1 L>H / H>L Min Max Min — 2.5 / 2.5 — — 2.5 / 2.5 — — 2.5 / 2.5 — ...
Page 98
... Max MSB, LSB 200 200 156 / 164 50 00 200 / 200 200 1.5 / 1.5 0.5 N/A Drive/slew Drive load rate select (pF) Max MSB, LSB 7 200 10 15 200 120 / 120 200 Freescale Semiconductor ...
Page 99
... Pull Up/Down — — (3.6 V max) Parameter D Classification 1 Propagation delay from internal signal to Pchannel/Nchannel on condition Slope at rising/falling edge. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Prop. delay (ns) Rise/fall edge (ns) L>H / H>L Min Max Min 5 15.4 / 15.4 144 / 155 ...
Page 100
... Table 52. AC specifications at 2.5 V VDDE Rise/fall edge (ns) Max Min Max 2.5/2.4 2.1/2.1 4.3/4.1 2.8/2.7 0.6/0.7 1.1/1.3 2.5/2.4 2.1/2.1 4.3/4.1 2.8/2.7 0.6/0.7 1.1/1.3 2.4/2.4 2.1/2.1 4.4/4.1 2.7/2.7 0.6/0.7 1.6/1.8 Drive/slew Drive load rate select Libraries (pF) MSB, LSB 5 111 6MDDR 20 5 111 6MDDR 20 5 111 6MDDR 20 Drive/slew Drive load rate select Libraries (pF) MSB, LSB 5 011 6MDDR 20 5 011 6MDDR 20 5 011 6MDDR 20 Freescale Semiconductor ...
Page 101
... AC specification for CMOS090_ddr library @ VDDE = 1.8 V Table 53. AC electrical specifications at 1.8 V VDD Prop. delay (ns) L>H / H>L Name C Min pad_st_acc C 1.4/1.4 1.7/1.7 1.4/1.5 1.7/1.7 1.4/1.5 1.7/1.7 1.4/1.5 1.7/1.8 pad_st_dq C 1.4/1.4 1.7/1.7 1.4/1.5 1.7/1.7 1.4/1.5 1.7/1.7 1.4/1.5 1.7/1.8 pad_st_clk C 1.4/1.4 1.6/1.6 1.4/1.4 1.7/1.7 1.4/1.4 1.6/1.6 1.4/1.5 1.7/1.8 Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Rise/fall edge (ns) Max Min Max 2.4/2.4 0.6/1.0 2.7/2.6 2.8/2.7 0.2/0.4 0.5/0.6 2.4/2.5 1.1/1.1 3.0/2.7 2.8/2.8 0.4/0.4 0.7/0.7 2.4/2.4 1.0/1.1 2.9/2.7 2.8/2.7 0.3/0.4 0.6/0.7 2.5/2.5 1.5/1.1 3.1/2.6 2.8/2.8 0.4/0.4 0.7/0.6 2.4/2.4 0.6/1.0 2.7/2.6 2.8/2.7 0.2/0.4 0.5/0.6 2.4/2.5 1.1/1.1 3.0/2.7 2.8/2.8 0.4/0.4 0.7/0.7 2.4/2.4 1.0/1.1 2.9/2.7 2.8/2.7 0.3/0.4 0.6/0.7 2.5/2.5 1.5/1.1 3.1/2.6 2.8/2.8 0.4/0.4 0.7/0.6 2.4/2.4 0.4/0.6 2.7/2.7 2.7/2.7 0.7/0.9 1.8/3.4 2.4/2.4 1.1/1.1 3.0/2.8 2.7/2.7 0.3/0.4 1.0/1.1 2.4/2.4 0.9/1.1 3.0/2.8 2.7/2.7 0.3/0.4 0.9/1.0 2.5/2.5 1.5/1.2 3.2/2.6 2.7/2.7 0.4/0.4 1.1/1.2 Drive/slew Drive load rate select Libraries (pF) MSB, LSB 5 000 6MDDR ...
Page 102
... Figure 16. JTAG Test Clock Input Timing 1 Min Max Unit 100 — — — — ns — — ns — — — — — — 3 3 -40 to 105 °C, and Freescale Semiconductor SpecID A1.1 A1.2 A1.3 A1.4 A1.5 A1.6 A1.7 A1.8 A1.9 A1.10 A1.11 A1.12 A1.13 ...
Page 103
... TCK TMS, TDI TDO Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Figure 17. JTAG Test Access Port Timing 6 8 103 ...
Page 104
... TCK 9 Output Signals 10 Output Signals Input Signals Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 104 12 Figure 18. JTAG Boundary Scan Timing 11 13 Freescale Semiconductor ...
Page 105
... Nexus Dual Data Rate is not supported. The timings are mentioned for dedicated pins on 416BGA. The max value for #2, 3 and 4 above, are 0.3 of tMCYC for shared nexus ports. MCKO MDO MSEO EVTO Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 55. Nexus Debug Port Timing Characteristic ...
Page 106
... LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with positive polarity. The sequence of events for active matrix interface timing is: Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 106 8 Figure 20. Nexus TCK Timing 10 11 Figure 21. Nexus TDI, TMS, TDO Timing Freescale Semiconductor ...
Page 107
... BP_H and FP_H parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the VSYN_PARA register Figure 22, the “LD[23:0]” signal is “line data,” an aggregation of the DCU’s RGB signals—R[0:7], G[0:7] and B[0:7]. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor LINE 2 LINE 3 LINE ...
Page 108
... BPH Figure 23. Horizontal sync timing Value Unit 31.25 ns PW_H PCP BP_H * t ns PCP FP_H * t ns PCP ns PCP ns t PCP PWV HSP BP_V * t ns HSP FP_V * t ns HSP ns HSP ns t HSP t FPH Invalid Data DELTA_X Freescale Semiconductor SpecID A3.1 A3.2 A3.3 A3.4 A3.5 A3.6 A3.7 A3.8 A3.9 A3.10 A3.11 ...
Page 109
... Intra bit skew is less than 2 ns. 3 Load for frequency MHz. 4 Load for display freq from MHz. 5 Parameter values guaranteed by design. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor t VSP BPV Figure 24. Vertical sync pulse 1,2,3,4 Min ...
Page 110
... HSYNC VSYNC DDE PCLK t CKH LD[23:0] Figure 25. LCD Interface Timing Parameters—Access Level Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 110 t t CHD CSU t CKL t t DSU DHD Freescale Semiconductor ...
Page 111
... SR D Transmitter Delay 3.3 V ± 10 -40 to +105 °C, unless otherwise specified. DDA A 2 All values need to be confirmed during device validation. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 58. RSDS Electrical Characteristics 1 Conditions — — — — — R ...
Page 112
... Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 112 Figure 26. TCON/RSDS Timing Diagram Freescale Semiconductor ...
Page 113
... CC Write Command to first DQS Latching Transition DQSS 10 DD7 t CC Data and Data Mask Output Setup (DQ-->DQS) OS relative to DQS (DDR Write Mode) Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 59. Pad mode configurations ipp_sre[2:0] Mode 000 1.8V LPDDR Half Speed 001 1.8V LPDDR Full Speed 010 1 ...
Page 114
... Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 114 DD_DR Parameter 13 14 /2). DD_DR ) plus some minor adjustments for process, temperature, SDCK parameter for clarity. CMV 5% (continued) Min Max Unit 1.0 — -(0.25*t - 0.25*t - SDCK SDCK 0.8) 0.8 /2. DD_DR Freescale Semiconductor ns ns ...
Page 115
... DDR SDRAM write timing. SD_CLK SD_CLK SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 SD_A[13:0] SD_DM SD_DQS SD_D[7:0] Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor DD1 DD2 DD5 CMD DD6 ROW COL WD1 WD2 WD3 WD4 Figure 27. DDR write timing DD3 DD7 ...
Page 116
... DD5 CL=2 CMD CL=2.5 ROW COL DQS Read Preamble Figure 28. DDR read timing = 50 Figure 29. DDR AC test load DD3 DD9 DQS Read Postamble DD10 RD1 RD2 RD3 RD4 DQS Read DQS Read Preamble Postamble RD1 RD2 RD3 RD4 V /2 DD_MEM_IO Freescale Semiconductor ...
Page 117
... C DC Input Logic Low il(dc Input Logic High ih(ac Input Logic Low il(ac Pad input Leakage in Current Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 61. SDR Timings Parameter Min C Data output Valid — (Write transaction) C Data output setup 2 DD1) DSK C Data output Hold 2 ...
Page 118
... Condition Min Nom — vddet-0.35 — — — — Vout=Voh -16.2 — Vout=Vol 16.2 — NOTE PAD Figure 31. SSTL_2 CLass II Test Load Max Units Notes — V — 0.35 V — mA vddet = 2.3V Voh = 1.95V — mA vddet = 2.3V Vol = 0.35V Vtt 70 ohms Z =70 td= 0.167ns 0 4pF Freescale Semiconductor SpecID A5.10 A5.11 A5.12 A5.13 ...
Page 119
... The SSTL_18 Class II output with ipp_sre[2:0] set to enabling sstl_2 1.8V DDR2 mode, at the destination, have a rise/fall time (10%-90%) between 0.4 ns and 1.0 ns over process, voltage, and temperature driving a 70 ohm transmission line with 0.167 ns Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Condi- Min Nom tion — ...
Page 120
... Ioh=-0.1mA vddet*0.9 — Iol=0.1mA — — Vtt 70 Z =70 td= 0.167ns 0 4pF Unit Max Notes s 1.9 V JESD79-4 1.32 V — vddet+0.3 V JESD79-4 vddet*0.3 V JESD79-4 vddet+0.3 V JESD79-4 vddet*0.2 V JESD79-4 — V JESD79-4 vddet*0.1 V JESD79-4 Figure Freescale Semiconductor SpecID A5.27 A5.28 A5.29 A5.30 A5.31 A5.32 A5.33 A5.34 A5.35 A5.36 27. ...
Page 121
... Description f D VIU2 pixel clock frequency PIX_CK t D VIU2 data setup time DSU t D VIU2 data hold time DHD Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor f PIX_CLK t DHD Figure 33. VIU2 timing diagram Table 65. VIU2 timing parameters Min Typ — — ...
Page 122
... Figure 34. IRQ and NMI Timing 1 Table 67. eMIOS timing Characteristic = 1. 1.32 V, VDDE_x = 3 5 DD12 Min. Max. Unit SpecID Value 200 — A7.1 ns 200 — A7.2 ns 400 — A7.3 ns Min. Max. Unit SpecID 2 value value 4 — t A8.1 CYC 1 — t A8.2 CYC = -40 to 105 °C, and Freescale Semiconductor ...
Page 123
... D CNRX Input Valid to CLKOUT Rising Edge (Setup CANSU Time) 1 FlexCAN timing specified MHz, V SYS 50 pF with SRC = 0b00. 2 Parameter values guaranteed by design. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 1 Table 68. FlexCAN timing Characteristic = 1. 1.32 V, VDDE_x = 3 5 DD12 Max. Min. value Unit SpecID value — ...
Page 124
... Freescale Semiconductor SpecID A11.1 A11.2 A11.3 A11.4 A11.5 A11.6 A11.7 A11.8 A11.9 A11.10 ...
Page 125
... Figure 35. DSPI Classic SPI Timing — Master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 36. DSPI Classic SPI Timing — Master, CPHA = 1 Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Last Data First Data Data ...
Page 126
... Figure 38. DSPI Classic SPI Timing — Slave, CPHA = 1 Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 126 First Data Data Last Data 7 8 Data Last Data First Data 9 5 Data First Data 7 8 Data First Data Last Data Last Data Freescale Semiconductor ...
Page 127
... Figure 39. DSPI Modified Transfer Format Timing — Master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 40. DSPI Modified Transfer Format Timing — Master, CPHA = 1 Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor First Data Last Data Data 10 9 ...
Page 128
... Figure 42. DSPI Modified Transfer Format Timing — Slave, CPHA = 1 Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 128 First Data Data Last Data 8 7 Data First Data Last Data 9 5 First Data Data 7 8 First Data Data Last Data Last Data Freescale Semiconductor ...
Page 129
... Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 2 C Input Timing Specifications—SCL and SDA Characteristic Min ...
Page 130
... Figure 45 Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 130 Figure 43 Input/Output Timing and Table 73: Parameter correspond to events as described Value Unit SpecID Min Typ Max 3.8 5.3 12.1 ns 7.6 9 13.2 ns –13 –8.5 –7.5 ns 0.5 0.7 1.0 ns 0.8 0.8 1.2 ns Table 73. Freescale Semiconductor A13.1 A13.2 A13.3 A13.4 A13.5 ...
Page 131
... Tcq SCK DO DI Note: Ts and Th correspond to QSPI_SMPR = 0x0000_000X. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 73. QuadSPI timing events Event Last address out Address captured at flash memory Data out from flash memory Ideal data capture edge Delayed data capture edge with QSPI_SMPR=0x0000_000X ...
Page 132
... Value Unit SpecID Min Typ Max 391 — 471 mV A14.1 1.17 — 1.4 V A14.2 606 — 844 ps A14.3 607 — 842 ps A14.4 — 2.65 — ns A14.5 — 2.47 — ns A14.6 s — 200 — A14.7 — — — ps A14.8 Freescale Semiconductor ...
Page 133
... Package mechanical data Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Figure 47. Rise/fall transition, part 1 Figure 48. Rise/fall transition, part –V Figure 49. Illustration of tr, tf, and V 0V Differential OD 133 ...
Page 134
... LQFP Figure 50. LQFP176 Mechanical Drawing (Part Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 134 Freescale Semiconductor ...
Page 135
... Figure 51. LQFP176 Mechanical Drawing (Part Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 135 ...
Page 136
... Figure 52. LQFP176 Mechanical Drawing (Part 5.2 208 LQFP Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 136 Freescale Semiconductor ...
Page 137
... Figure 53. LQFP208 Mechanical Drawing (Part Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 137 ...
Page 138
... Figure 54. LQFP208 Mechanical Drawing (Part Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 138 Freescale Semiconductor ...
Page 139
... Figure 55. LQFP208 Mechanical Drawing (Part Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor 139 ...
Page 140
... TEPBGA Figure 56. 416 TEPBGA Mechanical Drawing (Part Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 140 PRINT VERSION NOT TO SCALE Freescale Semiconductor ...
Page 141
... Figure 57. 416 TEPBGA Mechanical Drawing (Part Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor PRINT VERSION NOT TO SCALE 141 ...
Page 142
... Tape and reel status R = Tape and reel (blank) = Trays Qualification status P = Pre-qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow Speed Package (MHz) 176 LQFP (Pb free) 125 208 LQFP (Pb free) 125 416 TEPBGA (Pb free) 125 176 LQFP (Pb free) 125 Freescale Semiconductor ...
Page 143
... Revised the “System pin descriptions” table. Replaced the entire “DRAM interface pin summary” table. • In the “Nexus pins” table, added a PCR column. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 76. Revision history Description to V and added a footnote about the pin’s required termination. ...
Page 144
... For pin 59, changed PDI3(VIU3) to PDI3_VIU3. • For pin 148, deleted TCON0. • For pin 155, deleted DCULITE_G7. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 144 Table 76. Revision history (continued) Description (was min 1000 ns, is min 400 ns). NFRST (was max 40 ns, is FRST Freescale Semiconductor ...
Page 145
... Added “Parameter classification” section and accompanying table. Added “C” classification column and values to tables throughout the “Electrical characteristics“ section. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 76. Revision history (continued) Description of 125 MHz can be achieved only at temperatures up to 105 °C with ...
Page 146
... DD_DR from 4.5V and 5.5V to 3.0V and 3.6V, respectively. DD_DR (under “voltage drop” conditions) from 5.5V to 3.6V. DD_DR from 4.5V and 5. from 4.5V and 5.5V to 3.0V and 3.6V, respectively. DDE_B (VDDE max of that segment)“. “. “ and V . DD_DR DDM DDE_C and V , also referenced DDmin DDmax Freescale Semiconductor DDE_A ...
Page 147
... Removed “pad_fsr” and “pad_pci” parameters from “Supply leakage” table. Added Figure 28 - RSDS/TCON Timing Diagram Added four tables in “DRAM interface” section. Qorivva MPC5645S Microcontroller Data Sheet, Rev. 10 Freescale Semiconductor Table 76. Revision history (continued) Description “ entry of the “Recommended operating conditions (3.3 V)“ table, changed “V “ ...
Page 148
... IDDHALT value in “DC electrical characteristics” table. A Typ and Max values in “DC electrical characteristics” table. , from “DC electrical specifications at 3.3 V VDDE”, “DC electrical DD 60. Timings” section. . from 1. 1.4 V. DDPLL , and DDMAX DDHALT DDSTOP Table 22 in Section 4.7.3, “Low voltage domain Freescale Semiconductor ...
Page 149
... CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2009 - 2013 Freescale Semiconductor, Inc. ...