S9S12GN48F0CLH Freescale Semiconductor, S9S12GN48F0CLH Datasheet - Page 994
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S9S12GN48F0CLH
Manufacturer Part Number
S9S12GN48F0CLH
Description
16-bit Microcontrollers - MCU S12 Core,48kFlash,Au
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN48F0CLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12GN48F0CLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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96 KByte Flash Module (S12FTMRG96K1V1)
28.3.2.5
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU.
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
28.3.2.6
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
996
Offset Module Base + 0x0004
Reset
IGNSF
FDFD
FSFD
Field
CCIE
7
4
1
0
W
R
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Force Single Bit Fault Detect
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
Flash Configuration Register (FCNFG)
Flash Error Configuration Register (FERCNFG)
0
7
generated
Section
register is set (see
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section
28.3.2.8).
28.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
28.3.2.6)
= Unimplemented or Reserved
0
0
6
Figure 28-9. Flash Configuration Register (FCNFG)
Section
MC9S12G Family Reference Manual,
Table 28-13. FCNFG Field Descriptions
28.3.2.6)
0
0
5
—
The FSFD bit allows the user to simulate a single bit fault during Flash array
IGNSF
0
4
Description
0
0
3
Rev.1.23
0
0
2
Freescale Semiconductor
FDFD
0
1
Section
Section
28.3.2.7)
FSFD
28.3.2.7)
0
0
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