MAX199BC/D Maxim Integrated, MAX199BC/D Datasheet - Page 12
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MAX199BC/D
Manufacturer Part Number
MAX199BC/D
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet
1.MAX199AEAI-T.pdf
(16 pages)
Specifications of MAX199BC/D
Number Of Channels
8
Architecture
SAR
Conversion Rate
100 KSPs
Resolution
12 bit
Input Type
Single-Ended
Interface Type
Parallel
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Power Dissipation
762 mW
Number Of Converters
1
Voltage Reference
4.096 V
Select external clock mode by writing the control byte
with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR
timing relationships in internal and external acquisition
modes, with an external clock. A 100kHz to 2.0MHz
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)
Figure 8b. External Clock and WR Timing (External Acquisition Mode)
12
CLK
CLK
CLK
CLK
WR
WR
WR
WR
______________________________________________________________________________________
t
CWH
ACQMOD = "1"
ACQMOD = "1"
ACQMOD = "0"
ACQMOD = "0"
ACQUISITION STARTS
ACQUISITION STARTS
ACQUISITION STARTS
t
t
DH
DH
External Clock Mode
ACQUISITION STARTS
t
CWS
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
WR GOES HIGH WHEN CLK IS LOW
WR GOES HIGH WHEN CLK IS HIGH
external clock with 45% to 55% duty cycle is required
for proper operation. Operating at clock frequencies
lower than 100kHz will cause a voltage droop across
the hold capacitor, and subsequently degrade perfor-
mance.
ACQUISITION ENDS
t
ACQUISITION ENDS
CWH
ACQMOD = "0"
ACQUISITION ENDS
ACQUISITION ENDS
ACQMOD = "0"
t
CWS
CONVERSION STARTS
CONVERSION STARTS
CONVERSION STARTS
CONVERSION STARTS