MAX1363EUB Maxim Integrated, MAX1363EUB Datasheet - Page 19

• Manufacturer Part Number: MAX1363EUB
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1363EUB

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C, Serial
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: uMAX
• Maximum Power Dissipation: 444.4 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Table 9. Monitor-Mode Setup Data Format
Table 10. Alarm Reset, Scan Speed Register, and INT_EN Data Format
Table 11. Delay Settings
* When using delay = [0,0,0] in internal reference mode and
AIN3/REF configured as a REF output, the MAX1363/MAX1364
may exhibit a code-dependent gain error due to insufficient
internal reference drive. Gain error caused by this phenomenon
is typically less than 1%FSR (0.1µF C
larger C
V
as an analog input (see Table 4). Alternatively, choose delay bits
other than [0,0,0] to lower the conversion rate.
Table 12. Lower and Upper Threshold Data Format
X = Don’t care.
ACK = Acknowledge.
ALARM CH 0
DELAY 2 DELAY 1 DELAY 0
Alarm reset, scan
4-Channel, 12-Bit System Monitors with Programmable
DD
speed, INT_EN ,
BYTE
RESET
, as a reference or use an internal reference with AIN3/REF
0
0
0
0
1
1
1
1
1
2
3
0/1
(8 bits)
REF
. Avoid this gain error by using an external reference,
(MSB)
LT11
ALARM CH 1
0
0
1
1
0
0
1
1
UT7
LT3
B7
RESET
______________________________________________________________________________________
AIN0 thresholds
0/1
(24 bits)
0
1
0
1
0
1
0
1
LT10
UT6
LT2
B6
ALARM CH 2
RESET
Trip Window and SMBus Alert Response
0/1
REF
CONVERSION RATE
MONITOR-MODE
) and increases with a
(skip if differential mode, or
UT5
LT9
LT1
B5
CS1, CS0 < 1) (24 bits)
(ksps)
133.0*
AIN1 thresholds
66.5
33.3
16.6
ALARM CH 3
8.3
4.2
2.0
1.0
RESET
LT0 (LSB)
0/1
UT4
LT8
B4
(MSB)
UT11
UT3
DELAY 2
LT7
B3
clearing all alarms or by initiating an SMBus alert during
an alarm condition (see the SMBus Alert section).
The Delay 2, Delay 1, Delay 0 bits set the speed of
monitoring by changing the delay between conver-
sions. Delay 2, 1, 0 = 000 sets the maximum possible
speed; 001 divides the maximum speed by ~2.
Increasing delay values further divides the previous
speed by two.
INT_EN controls the open-drain INT output. Set INT_EN
to 1 to enable the hardware interrupt. Set INT_EN to 0
to disable the hardware interrupt output. The INT output
tri-states when disabled or when there are no alarms.
The master can also poll the alarm status register at
any time to check the alarm status.
Repeat clocking channel threshold data up to the chan-
nel programmed by CS1 and CS0 (Table 12). For differ-
ential input mode, omit odd channels; the lower and
upper threshold data applies to channel pairs. There is
no need to clock in dummy data for odd (or even)
channels (Table 6).
To disable alarming on a specific channel, set the lower
threshold to 0x800 and the upper threshold to 0x7FF for
bipolar mode, or set the lower threshold to 0x000 and
the upper threshold to 0xFFF for unipolar mode.
0/1
AIN2 thresholds (skip if
CS1, CS0 < 2)
UT10
UT2
LT6
(24 bits)
B2
DELAY 1
0/1
UT9
UT1
LT5
B1
AIN3 thresholds (skip if differential
UT0 (LSB)
DELAY 0
mode, or CS1, CS0 < 3)
UT8
LT4
B0
0/1
(24 bits)
ACKNOWLEDGE
ACK
ACK
ACK
INT_EN
0/1
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