MAX1202AEPP Maxim Integrated, MAX1202AEPP Datasheet - Page 17

• Manufacturer Part Number: MAX1202AEPP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1202AEPP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
The SHDN pin places the converter into full power-down
mode. Unlike the software power-down modes, conver-
sion is not completed; it stops coincidentally with SHDN
being brought low. There is no power-up delay if an
external reference, which is not shut down, is used.
SHDN also selects internal or external reference com-
pensation (Table 7).
The MAX1202/MAX1203’s automatic power-down
modes can save considerable power when operating
at less than maximum sample rates. The following sec-
tions discuss the various power-down sequences.
Figure 14a depicts MAX1202 power consumption for one
or eight channel conversions using full power-down
mode and internal reference compensation. A 0.01µF
DOUT
SCLK
DIN
SSTRB
CS
DOUT
SCLK
DIN
CS
S
500 Conversions per Channel per Second
S
CONTROL BYTE 0
1
______________________________________________________________________________________
CONTROL BYTE 0
Power-Down Sequencing
Hardware Power-Down
Lowest Power at up to
5V, 8-Channel, Serial, 12-Bit ADCs
8
B11
B10
B11
B9
B10
B8
CONVERSION RESULT 0
B9
B7
B8
B6
B7
CONVERSION RESULT 0
B5
B6
B4
S
B5
1
with 3V Digital Interface
B3
B4
B3
bypass capacitor at REFADJ forms an RC filter with the
internal 20kΩ reference resistor, with a 0.2ms time con-
stant. To achieve full 12-bit accuracy, 10 time constants
(or 2ms in this example) are required for the reference
buffer to settle. When exiting FULLPD, waiting this 2ms in
FASTPD mode (instead of just exiting FULLPD mode and
returning to normal operating mode) reduces power con-
sumption by a factor of 10 or more (Figure 13).
Figure 14b shows power consumption with external-
reference compensation in fast power-down, with one
and eight channels converted. The external 4.7µF com-
pensation requires a 50µs wait after power-up. This cir-
cuit combines fast multichannel conversion with the
lowest power consumption possible. Full power-down
mode can increase power savings in applications where
the MAX1202/MAX1203 are inactive for long periods of
time, but where intermittent bursts of high-speed conver-
sion are required.
B2
CONTROL BYTE 1
B2
S
B1 B0
B1 B0
CONTROL BYTE 1
8
Lowest Power at Higher Throughputs
B11
B10
B9
CONVERSION RESULT 1
B8
B7
B11
B6
CONVERSION RESULT 1
B10
B5
S
1
B9
B4
CONTROL BYTE 2
B8
B3 B2
B7
B6
B1
B5
B0
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