MAX1033BEUP/GG8 Maxim Integrated, MAX1033BEUP/GG8 Datasheet - Page 18

• Manufacturer Part Number: MAX1033BEUP/GG8
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1033BEUP/GG8

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 115 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended/Differential
• Snr: 85 dB
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 879 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

8- and 4-Channel, ±3 x V
Multirange Inputs, Serial 14-Bit ADCs
The MAX1032/MAX1033 differential common-mode
range (V
obtain valid conversion results. The differential com-
mon-mode range is defined as:
In addition to the common-mode input voltage limita-
Table 3. Input Data Word Formats
Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0)
Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)
18
Conversion-Start Byte
(Tables 4 and 5)
Analog-Input Configuration Byte
(Table 2)
Mode-Control Byte
(Table 7)
C2
C2
CHANNEL-SELECT BIT
CHANNEL-SELECT BIT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
______________________________________________________________________________________
CMDR
V
OPERATION
CMDR
Differential Common-Mode Range
C1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
) must remain within -14V to +9V to
=
(
C0
C0
CH
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
_
+
)
+
2
CH0
CH0
(
+
+
CH
(START)
_
−
D7
1
1
1
)
CH1
CH1
+
-
M2
D6
C2
C2
CH2
CH2
+
+
REF
M1
D5
C1
C1
tions, each individual analog input must be limited to
±16.5V with respect to AGND1.
The range-select bits R[2:0] in the analog input config-
uration bytes determine the full-scale range for the cor-
responding channel (Tables 2 and 6). Figures 9, 10,
and 11 show the valid analog input voltage ranges for
the MAX1032/MAX1033 when operating with FSR = ±3
x V
respectively. The shaded area contains the valid com-
mon-mode voltage ranges that support the entire FSR.
CH3
CH3
+
-
REF
RESERVED
RESERVED
RESERVED
RESERVED
CHANNEL
CHANNEL
/2, FSR = ±3 x V
M0
D4
C0
C0
CH4
CH4
DATA BIT
+
+
DIF/SGL
D3
0
1
CH5
CH5
+
-
REF
D2
R2
CH6
CH6
, and FSR = ±6 x V
0
0
+
+
CH7
CH7
D1
R1
0
0
+
-
AGND1
AGND1
D0
R0
0
0
-
-
-
-
-
-
-
-
REF
,