MAX1142BCAP Maxim Integrated, MAX1142BCAP Datasheet - Page 8

• Manufacturer Part Number: MAX1142BCAP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1142BCAP

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 82 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

14-Bit ADC, 200ksps, +5V Single-Supply
with Reference
8
PIN
10
11
12
13
14
15
16
17
18
19
20
_______________________________________________________________________________________
1
2
3
4
5
6
7
8
9
REFADJ
SSTRB
NAME
DGND
DGND
AGND
SHDN
AGND
DOUT
AV
SCLK
DV
CREF
REF
RST
DIN
AIN
CS
P2
P1
P0
DD
DD
Reference Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode, the reference buffer provides a +4.096V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to AV
AGND with a 2.2µF capacitor when using the internal reference.
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to AGND with 0.22µF. When using an
external reference, connect REFADJ to AV
Analog Ground. This is the primary analog ground (Star Ground).
Analog Supply 5V 5%. Bypass AV
Digital Ground
Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.
User-Programmable Output 2
User-Programmable Output 1
User-Programmable Output 0
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period
before the MSB decision. It is high impedance when CS is high in external clock mode.
Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.
Each bit is clocked out of DOUT at the falling edge of SCLK.
Reset Inp ut. D r i ve RST l ow to p ut the d evi ce i n the p ow er - on d efaul t m od e. S ee the P ow er - O n Reset secti on.
Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated
on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed.
Digital Ground. Connect to pin 5.
Digital Supply 5V 5%. Bypass DV
Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK.
Chip Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT is high-impedance.
In external clock mode SSTRB is high-impedance when CS is high.
Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with 1µF.
Analog Ground. Connect pin 19 to pin 3.
Analog Input
DD
DD
to DGND (pin 14) with a 0.1µF capacitor.
to AGND (pin 3) with a 0.1µF capacitor.
DD
to disable the internal bandgap reference.
FUNCTION
Pin Description
DD
. Bypass to