MCF51JF64VHS Freescale Semiconductor, MCF51JF64VHS Datasheet - Page 47

• Manufacturer Part Number: MCF51JF64VHS
• Description: 32-bit Microcontrollers - MCU COLDFIRE V1 64KFLASH
• Manufacturer: Freescale Semiconductor

Specifications of MCF51JF64VHS

• Rohs: yes
• Core: ColdFire V1
• Processor Series: MCF51JF128
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: QFN-44
• Mounting Style: SMD/SMT

1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I
6.8.4 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices.
All timing is shown with respect to 20% V
input signal transitions of 3 ns and a 50 pF maximum load on all SPI pins. All timing
assumes slew rate control is disabled and high drive strength is enabled for SPI output
pins.
Freescale Semiconductor, Inc.
V
V
Symbol
Reg33out
Reg33out
C
Num.
ESR
I
LIM
OUT
1
2
3
4
5
Regulator output voltage — Input supply
(VREGIN) > 3.6 V
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
External output capacitor
External output capacitor equivalent series
resistance
Short circuit current
Description
t
Symbol
WSPSCK
t
SPSCK
t
• Run mode
• Standby mode
t
Lead
f
Lag
op
Table 32. USB VREG electrical specifications
Frequency of operation
SPSCK period
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Description
(continued)
Table 33. SPI master mode timing
MCF51JF128 Data Sheet, Rev. 6, 01/2012.
Table continues on the next page...
DD
and 70% V
1.76
Min.
2.1
2.1
—
3
1
f
BUS
t
2 x t
BUS
Typ.
290
Min.
3.3
2.8
2.2
DD
1/2
1/2
—
—
/2048
BUS
- 30
1
, unless noted, as well as
2048 x
1024 x
f
Max.
Max.
BUS
8.16
t
t
100
3.6
3.6
3.6
BUS
BUS
—
—
—
/2
Communication interfaces
t
t
SPSCK
SPSCK
Unit
Unit
mΩ
mA
μF
Hz
ns
ns
V
V
V
as defined
in
f
Comment
bus clock
BUS
t
BUS
Load
Notes
Table
f
BUS
—
—
—
2
is the
= 1/
.
8.
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