MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 222
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MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Functional Description and Application Information
4.31.3.2.7
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are
allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match.
The three debug state control registers are located at the same address in the register address map (0x0027). Each register can
be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag
register (DBGMFR).
4.31.3.2.7.1
Table 278. Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in
State1. The matches refer to the match channels of the comparator match control logic as depicted in
in
comparator enable bit in the associated DBGXCTL control register.
Table 279. DBGSCR1 Field Descriptions
Freescale Semiconductor
Address: 0x0027
Reset
Section 4.31.3.2.8.1, “Debug Comparator Control Register
SC[2:0]
W
R
Field
2–0
Table 276. CNT Decoding Table (continued)
These bits select the targeted next state whilst in State1, based upon the match event.
0
0
7
TBF
Debug State Control Registers
Debug State Control Register 1 (DBGSCR1)
1
Table 277. State Control Register Access Encoding
0
0
6
CNT[5:0]
000001
111110
…
…
COMRV
00
01
10
11
5
0
0
oldest data has been overwritten by most recent data
Visible State Control Register
0
0
4
(DBGXCTL)"”. Comparators must be enabled by setting the
Description
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
0
0
3
64 lines valid,
Description
SC2
S12S Debug (S12SDBGV1) Module
0
2
Figure 69
SC1
1
0
and described
MM912F634
SC0
0
0
222
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