MK20DN128VLF5 Freescale Semiconductor, MK20DN128VLF5 Datasheet - Page 48

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MK20DN128VLF5

Manufacturer Part Number
MK20DN128VLF5
Description
ARM Microcontrollers - MCU KINETIS 128K
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK20DN128VLF5

Rohs
yes
Core
ARM Cortex M4
Processor Series
K20
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
128 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MK20DN128VLF5
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Peripheral operating requirements and behaviors
6.8.5 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
48
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
range the maximum frequency of operation is reduced.
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 34. Master mode DSPI timing (full voltage range)
Figure 17. DSPI classic SPI timing — master mode
DS7
DS3
Description
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
First data
DS8
First data
DS5
DS2
Data
Data
DS6
(t
(t
(t
BUS
BUS
SCK
4 x t
DS1
Last data
1.71
19.1
Min.
-1.2
4
4
0
/2) - 4
x 2) −
x 2) −
BUS
Last data
(t
DS4
SCK/2)
Max.
12.5
3.6
8.5
+ 4
Freescale Semiconductor, Inc.
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
Notes
1
2
3

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