W65C816S6PG-14 Western Design Center (WDC), W65C816S6PG-14 Datasheet
W65C816S6PG-14
Specifications of W65C816S6PG-14
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W65C816S6PG-14 Summary of contents
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Sept 13, 2010 W65C816S 8/16–bit Microprocessor ...
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WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made ...
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INTRODUCTION ...................................................................................................... 7 1.1 Features of the W65C816S ......................................................................................................... 7 2 W65C816S FUNCTIONAL DESCRIPTION ............................................................. 8 2.1 Instruction Register (IR) ............................................................................................................. 8 2.2 Timing Control Unit (TCU) .......................................................................................................... 8 2.3 Arithmetic and Logic ...
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Direct Indexed with Y-d,y ........................................................................................................ 22 3.5.13 Direct Indirect Indexed-(d),y .................................................................................................... 22 3.5.14 Direct Indirect Long Indexed-[d],y ........................................................................................... 23 3.5.15 Direct Indirect Long-[d] ............................................................................................................ 23 3.5.16 Direct Indirect-(d) ..................................................................................................................... 23 3.5.17 Direct-d .................................................................................................................................... 24 3.5.18 Immediate-# ............................................................................................................................. 24 3.5.19 ...
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HARD CORE MODEL............................................................................................ 56 8.1 W65C816 Core Information ...................................................................................................... 56 9 SOFT CORE RTL MODEL .................................................................................... 56 9.1 W65C816 Synthesizable RTL-Code in Verilog HDL ............................................................... 56 10 ORDERING INFORMATION ............................................................................... 57 ...
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Table 2-1 W65C816S Microprocessor Programming Model ...................................................................... 11 Table 2-2 Pin Function Table ..................................................................................................................... 14 Table 3-1 Addressing Mode Summary ...................................................................................................... 26 Table 4-1 Absolute Maximum Ratings ....................................................................................................... 27 Table 4-2 W65C816S AC Characteristics .................................................................................................. 29 Table 5-1 W65C816S Instruction ...
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INTRODUCTION The W65C816S is a low power cost sensitive 8/16-bit microprocessor. The variable length instruction set and manually optimized core size makes the W65C816S an excellent choice for low power System-on-Chip (SoC) designs. The Verilog RTL model is available ...
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W65C816S FUNCTIONAL DESCRIPTION The W65C816S provides the design engineer with upward software compatibility from 8-bit W65C02S in applications to 16-bit system application. In Emulation mode, the W65C816S offers many advantages, including full software compatibility with W65C02S coding. Internal organization ...
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Direct (D) The 16-bit Direct Register provides an address offset for all instructions using direct addressing. The effective Direct Address is formed by adding the 8-bit instruction Direct Address field to the Direct Register. The Direct Register is initialized ...
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A0-A7 A8-A15 D0-D7 BE Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram INDEX X (16 BITS) INDEX Y (16 BITS) STACK POINTER (S) (16 BITS) ALU (16 BITS) TRANSFER SWITCHES ACCUMULATOR (C) (16 BITS) (A) (8 BITS) (B) (8 BITS) ...
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Table 2-1 W65C816S Microprocessor Programming Model 11 ...
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Pin Function Description VPB RDY ABORT IRQB MLB NMIB VPA VDD A10 A11 Figure 2-2 W65C816S 40 Pin DIP Pinout NMIB VPA VDD ...
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NMIB VPA VDD Figure 2-4 W65C816S 44 PIN QFP Pinout \ RWB 32 3 VDD W65C816S ...
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A0-A15 ABORTB BE PHI2 D0-D7 E IRQB MLB MX NC NMIB RDY RESB RWB VDA VPB VPA VDD VSS 2.13 Abort (ABORTB) The Abort negative pulse active input is used to abort instructions (usually due to an Address Bus condition). ...
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Data/Bank Address Bus (D0-D7) The Data/Bank Address Bus pins provide both the Bank Address and Data. The bank address is present during the first half of a memory cycle, and the data value is read or written during the ...
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Non-Maskable Interrupt (NMIB) A negative transition on the non-maskable Interrupt input initiates an interrupt sequence. A high to low transition initiates an interrupt sequence after the current instruction is completed. The Wait for Interrupt instruction may be executed to ...
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Reset (RESB) The Reset active low input is used to initialize the microprocessor and start program execution. The Reset input buffer has hysteresis such that a simple R-C timing circuit may be used with the internal pull-up device. The ...
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ADDRESSING MODES The W65C816S is capable of directly addressing 16 MBytes of memory. This address space has special significance within certain addressing modes, as follows: 3.1 Reset and Interrupt Vectors The Reset and Interrupt Vectors use the majority of ...
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Absolute-a With Absolute addressing the second and third bytes of the instruction form the low order 16 bits of the effective address. The Data Bank Register contains the high order 8 bits of the operand address. 3.5.2 Absolute Indexed ...
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Absolute Indirect-(a) With Absolute Indirect addressing the second and third bytes of the instruction form an address to a pointer in Bank 0. The Program Counter is loaded with the first and second bytes at this pointer. With the ...
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Block Move-xyc Block Move (xyc) addressing is used by the Block Move instructions. The second byte of the instruction contains the high-order 8 bits of the destination address and the Y Index Register contains the low- order 16 bits ...
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Direct Indexed with X-d,x With Direct Indexed with X (d,x) addressing the second byte of the instruction is added to the sum of the Direct Register and the X Index Register to form the 16-bit effective address. The operand ...
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Direct Indirect Long Indexed-[d],y With Direct Indirect Long Indexed ([d],y) addressing the 24-bit base address is pointed to by the sum of the second byte of the instruction and the Direct Register. The effective address is this 24-bit base ...
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Direct-d With Direct (d) addressing the second byte of the instruction is added to the Direct Register (D) to form the effective address. An additional cycle is required when the Direct Register is not page aligned (DL not equal ...
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Stack Relative-d,s With Stack Relative (d,s) addressing the low-order 16 bits of the effective address is formed from the sum of the second byte of the instruction and the stack pointer. The high-order 8 bits of the effective address ...
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Table 3-1 Addressing Mode Summary Address Mode Absolute Absolute Indexed Indirect (Jump) Absolute Indirect (Jump) Absolute Long Absolute Long, X Absolute, X Absolute, Y Accumulator Block Move (xyc) Direct Direct Indexed Indirect (d,x) Direct Indirect Direct Indirect Indexed (d),y Direct ...
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TIMING, AC AND DC CHARACTERISTICS 4.1 Absolute Maximum Ratings This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. ...
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Figure 4-1 IDD vs. VDD Figure 4-2 F Max vs. VDD 28 ...
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Table 4-2 W65C816S AC Characteristics 5.0 +/- 5% Symbol Parameter Min 4.75 VDD 70 tCYC Cycle Time 35 tPWL Clock Pulse Width Low 35 tPWH Clock Pulse Width High tF,tR Fall Time, Rise Time 10 tAH A0-A15 Hold Time tADS ...
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PHI2 RWB, MLB, VPB A0-A15, VDA VPA t ADS READ DATA, BA0-BA7 t DHR t BAS WRITE DATA, BA0-BA7 t DHW IRQB, NMIB, RESB, RDY ABORTB M M Timing measurement points are ...
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OPERATION TABLES Table 5-1 W65C816S Instruction Set-Alphabetical Sequence 1. ADC Add Memory to Accumulator with Carry 2. AND "AND" Memory with Accumulator 3. ASL Shift One Bit Left, Memory or Accumulator 4. BCC Branch on Carry Clear (C=0) 5. ...
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Table 5-2 Emulation Mode Vector Locations (8-bit Mode) Address 00FFFE,F 00FFFC,D 00FFFA,B 00FFF8,9 00FFF6,7 00FFF4,5 00FFF2,3 00FFF0,1 Table 5-3 Native Mode Vector Locations (16-bit Mode) Address 00FFEE,F 00FFEC,D 00FFEA,B 00FFE8,9 00FFE6,7 00FFE4,5 00FFE2,3 00FFE0,1 The VP output is low during ...
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BRK ORA COP ORA TSB 0 s (d,x) s d,s d 7,2 6,2 7,2 4,2 5,2 BPL ORA ORA ORA TRB 1 r (d),y (d) (d,s),y d 2,2 5,2 5,2 7,2 5,2 ...
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Table 5-5 Operation, Operation Codes, and Status Register Operation Addressing Mode A+M+C→ ADC A^M→ AND C←15/7 6 … 10 ← ASL Branch BCC ...
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Operation Addressing Mode → LDX M → LDY 0 → 15/7 6 … → LSR M→M NEGATIVE MVN* M→M POSITIVE MVP* No Operation ...
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Operation Addressing Mode → STY 00 → STZ A → X TAX A → Y TAY C → D TCD* C → S TCS* D → C TDC* 1C TRB ...
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Table 5-6 Addressing Mode Symbol Table Symbol Addressing Mode # immediate A accumulator r program counter relative rl program counter relative long I implied s stack d direct d,x direct indexed with x d,y direct indexed with y (d) direct ...
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Table 5-7 Instruction Operation (continued on following 6 pages) Address Mode 1a. Absolute a ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX LDY ORA, SBC, STA, STX, STY, STZ, 18 OpCodes, 3 bytes, 4 & 5 cycles 1b. Absolute ...
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Address Mode 4a. Absolute Long al ADC, AND, CMP, EOR, LDA, ORA, SBC, STA, 8 OpCodes, 4 bytes, 5 & 6 cycles 4b. Absolute Long (JUMP) al JMP 1 OpCode, 4 bytes, 4 cycles 4c. Absolute Long (JUMP to Subroutine ...
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Address Mode 9a. Block Move Negative (backward) xyc MVN 1 Op Code N-2 3 bytes Byte 7 cycles C=2 x=Source Address y=Destination c=# of bytes to move-1 x,y Increment FFFFF Source End Dest. End Source Start N Byte 000000 C=0 ...
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Address Mode 10a. Direct d ADC AND BIT, CMP, CPX, CPY ,EOR, LDA, LDX, LDY, ORA, SBC, STA, STX, STY, STZ 16 OpCodes, 2 bytes & 5 cycles 10b. Direct (R-M-W)d ASL, DEC, INC, LSR, ROL, ROR, TRB, ...
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Address Mode Note 16a. Direct, X d,x ADC, AND, BIT, CMP, EOR, LDA LDY, ORA, SBC, STA, STY, STZ, (2) 12 OpCodes,2 bytes, 4,5,and 6 cycles (1) 16b. Direct, X (R-M-W) d,x ASL, DEC, INC, LSR, ROL, ROR, 6 OpCodes, ...
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Address Mode 20. Relative r BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC,BVS 9 OpCodes, 2 bytes, 2,3 and 4 cycles 21. Relative Long rl BRL 1 OpCode, 3 bytes, 4 cycles 22a. Stack s ABORT, IRQ, NMI, RES 4 ...
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Address Mode 22g. Stack s RTI 1 Op Code, 1 byte, 6 and 7 cycles (different order fromN6502) 22h. Stack s RTS 1 OpCode, 1 byte, 6 cycles 22i. Stack s RTL 1 Op Code, 1 byte, 6 cycles 22j. ...
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Notes: Be aware that notes #4-7, 9 and 10 apply to the W65C02S and W65C816S. All other notes apply to the W65C816S only. 1. Add 1 byte (for immediate only) for M=0 or X=0 (i.e. 16-bit data), add 1 cycle ...
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Figure 5-1 Bank Address Latching Circuit 46 ...
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RECOMMENDED W65C816S ASSEMBLER SYNTAX STANDARDS 6.1 Directives Assembler directives are those parts of the assembly language source program which give directions to the assembler; this includes the definition of data area and constants within a program. This standard excludes ...
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Table 6-1 Alternate Mnemonics 6.3.2.4 JSL should be recognized as equivalent to JSR when it is specified with a long absolute address forced. JML is equivalent to JMP with long addressing forced. 6.3.3 The Operand Field The operand field may ...
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Addressing Mode Format Immediate #d #a #al #EXT #<d #<a #<al #<EXT #>d #>a #>al #>EXT #^d #^a #^al #^EXT Absolute ! !al !EXT EXT Absolute Long >d >a >al al >EXT Direct Page d <d <a <al ...
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Note that the operand does not determine whether or not immediate address loads one or two bytes, this is determined by the setting of the status register. This forces the requirement for a directive or directives that tell the ...
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Caveats Compatibility Issue NMOS 6502 Always Page (Stack) bits Always Page Index Reg) Always less than 256 ie 8 Bits Always Page Index Reg) Always less than 256 ie 8 ...
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Stack Addressing When in the Native mode, the Stack may use memory locations 000000 to 00FFFF. The effective address of Stack, Stack Relative, and Stack Relative Indirect Indexed addressing modes will always be within this range. In the Emulation ...
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DB/BA operation when RDY is Pulled Low When RDY is low, the Data Bus is held in the data transfer state (i.e. PHI2 high). The Bank address external transparent latch should be latched on the rising edge of the ...
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Binary Mode The Binary Mode is set whenever a hardware or software interrupt is executed. The D flag within the Status Register is cleared to zero. 7.13 Wait for Interrupt (WAI) Instruction The WAI instruction pulls RDY low and ...
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Interrupt Priorities The following interrupt priorities will be in effect should more than one interrupt occur at the same time: Priority Highest Priority 1. RESB Lower 2. Abortb’ Lower 3 NMIB Lowest 4 IRQB 7.20 Transfers from 8-Bit to ...
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HARD CORE MODEL 8.1 W65C816 Core Information • The W65C816S core uses the same instruction set as the W65C816S • The only functional difference between the W65C816S and W65C816S core is the RDY pin. The W65C816S RDY pin is ...
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ORDERING INFORMATION Description W65C = standard product Product Identification Number Foundry Process 6 = .6u Package P = Plastic Dual-In-Line, 40 pins PL = Plastic Leaded Chip Carrier, 44 pins RoHS/Green Compliance G = RoHS/Green Compliant (Wafer and Packaging) ...