MK50DX256CLK10 Freescale Semiconductor, MK50DX256CLK10 Datasheet
MK50DX256CLK10
Specifications of MK50DX256CLK10
Related parts for MK50DX256CLK10
MK50DX256CLK10 Summary of contents
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... Freescale Semiconductor Data Sheet: Technical Data K50 Sub-Family Supports the following: MK50DX256CLK10 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 85°C • Performance – 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1 ...
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... USB VREG electrical specifications......................59 6.8.4 DSPI switching specifications (limited voltage range)....................................................................59 6.8.5 DSPI switching specifications (full voltage range).61 6.8.6 I2C switching specifications..................................63 6.8.7 UART switching specifications..............................63 6.8.8 I2S/SAI Switching Specifications..........................63 6.9 Human-machine interfaces (HMI)......................................69 6.9.1 TSI electrical specifications...................................69 7 Dimensions...............................................................................70 7.1 Obtaining package dimensions.........................................70 8 Pinout........................................................................................71 Freescale Semiconductor, Inc. ...
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... K50 Signal Multiplexing and Pin Assignments..................71 8.2 K50 Pinouts.......................................................................74 K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. 9 Revision History........................................................................75 3 ...
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... Description • Fully qualified, general market flow • Prequalification • K50 • Cortex-M4 w/ DSP • Cortex-M4 w/ DSP and FPU • Program flash only • Program flash and FlexMemory Table continues on the next page... Values Freescale Semiconductor, Inc. ...
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... An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Description • • • ...
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... Example This is an example of an attribute: Symbol Description CIN_D Input capacitance: digital pins K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 6 Min. Max. 0.9 1.1 Min. Max. 10 130 Min. Max. — 7 Unit V Unit µA Unit pF Freescale Semiconductor, Inc. ...
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... Result of exceeding a rating Measured characteristic K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating Terminology and guidelines Max. ...
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... Normal operating range Degraded operating range - No permanent failure - No permanent failure - Correct operation - Possible decreased life - Possible incorrect operation Operating (power on) Handling range No permanent failure Handling (power off) Fatal range Expected permanent failure ∞ Fatal range Expected permanent failure ∞ Freescale Semiconductor, Inc. ...
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... Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol T Ambient temperature A V 3.3 V supply voltage DD K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Terminology and guidelines Max. ...
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... K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 10 Min. –55 — Min. — Min. -2000 -500 -100 Table continues on the next page... Max. Unit Notes 150 °C 1 260 °C 2 Max. Unit Notes 3 — 1 Max. Unit Notes +2000 V 1 +500 V 2 +100 mA Min. Max. Unit –0.3 3.8 V Freescale Semiconductor, Inc. ...
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... Nonswitching electrical specifications K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. General Min. Max. Unit — ...
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... DD -V )/|I |. The positive injection current limiting resistor is AIO_MIN IN IC Max. Unit Notes 3.6 V 3.6 V 0.1 V 0.1 V 3.6 V — — 0.35 × 0.3 × — — — +5 — mA +25 — V — greater than V IN AIO_MIN Freescale Semiconductor, Inc ...
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... Internal low power oscillator period — factory LPO trimmed 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description V Falling VBAT supply POR detect voltage POR_VBAT K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. supply LVD and POR operating requirements Min. 0.8 2.48 2.62 2.72 2.82 2.92 — 1.54 1 ...
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... Vinput = min and Vinput = and VLLSx→RUN recovery times in the following table Max. Unit Notes — V — V — V — V 100 mA 0.5 V 0.5 V 0.5 V 0.5 V 100 mA 1 μA 1 0.025 μ μA 50 kΩ kΩ 3 Freescale Semiconductor, Inc. ...
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... I Very-low-power run mode current at 3.0 V — all DD_VLPR peripheral clocks disabled I Very-low-power run mode current at 3.0 V — all DD_VLPR peripheral clocks enabled K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. — DD — — — — — — ...
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... Table continues on the next page... Max. Unit Notes — 1. 435 μA 2000 μA 4000 μA 9 19.9 μA 105 μA 500 μ μA 43 μA 230 μA 5.4 μA 35 μA 128 μA 9 μA 28 μA 95.5 μA 0.22 μA 0.64 μA 3.2 μA Freescale Semiconductor, Inc. ...
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... USB regulator disabled • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. Typ. Max. Unit — ...
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... MHz (crystal OSC K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 18 Frequency Typ. band (MHz) 0.15–50 23 50–150 27 150–500 28 500–1000 14 0.15–1000 MHz 48MHz SYS BUS Unit Notes dBμ dBμV dBμV dBμV — Freescale Semiconductor, Inc. ...
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... System and core clock SYS f Bus clock BUS FB_CLK FlexBus clock f Flash clock FLASH f External reference clock ERCLK K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Table 8. Capacitance attributes Min. Normal run mode — 20 — — — — 1 VLPR mode — — ...
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... Max. Unit 1.5 — Bus clock cycles 100 — — ns 100 — — Bus clock cycles — — — — — — — — Freescale Semiconductor, Inc. Notes Notes ...
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... Four-layer (2s2p) R θJA Single-layer (1s) R θJMA Four-layer (2s2p) R θJMA — R θJB — R θJC K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Description 80 LQFP Thermal 50 resistance, junction to ambient (natural convection) Thermal 35 resistance, junction to ambient (natural convection) Thermal 39 resistance, junction to ambient (200 ft./ min ...
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... Figure 3. TRACE_CLKOUT specifications K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 22 Description 80 LQFP Thermal 2 characterization parameter, junction to package top outside center (natural convection) Unit Notes °C/W 4 Min. Max. Unit Frequency dependent MHz 2 — — ns — — — — ns Freescale Semiconductor, Inc. ...
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... TRST assert time J14 TRST setup time (negation) to TCLK high Table 14. JTAG full voltage range electricals Symbol Description Operating voltage K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Ts Th Table continues on the next page... Ts Th Min. ...
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... Figure 5. Test clock input timing Min. Max. Unit MHz 1/J1 — — — ns 12.5 — ns — — — ns — — — ns 1.4 — ns — 22.1 ns — 22.1 ns 100 — — Freescale Semiconductor, Inc. ...
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... Data inputs Data outputs Data outputs Data outputs Figure 6. Boundary scan (JTAG) timing TCLK TDI/TMS TDO TDO TDO K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J11 J12 J11 Figure 7. Test Access Port timing J5 J6 ...
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... Table continues on the next page... Max. Unit Notes — kHz — 39.0625 kHz ± 0 dco ± 0 dco ± dco ± dco 4 — MHz — 5 MHz — — kHz — — kHz Freescale Semiconductor, Inc. ...
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... MHz vco • 100 MHz vco D Lock entry frequency tolerance lock D Lock exit frequency tolerance unl K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. FLL 31.25 20 20.97 640 × f fll_ref 40 41.94 1280 × f fll_ref 60 62.91 1920 × ...
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... Typ. 1.71 — — 500 — 200 — 300 — 950 — 1.2 — 1.5 Table continues on the next page... Max. Unit Notes -6 150 × 1075( pll_ref Max. Unit Notes 3 — nA — μA — μA — μA — mA — mA Freescale Semiconductor, Inc. ...
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... When low power mode is selected The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — ...
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... NOTE Min. 1.71 — Table continues on the next page... Max. Unit Notes 40 kHz 8 MHz 32 MHz 50 MHz — — ms — ms — ms Typ. Max. Unit — 3.6 V 100 — MΩ Freescale Semiconductor, Inc. ...
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... Sector Erase high-voltage time hversscr t Erase Block high-voltage time for 256 KB hversblk256k 1. Maximum time based on expectations at cycling end-of-life. K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — — 700 and V specifications do not apply. The voltage of the applied ...
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... Freescale Semiconductor, Inc ...
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... Average current adder during high voltage DD_PGM flash programming operation I Average current adder during high voltage DD_ERS flash erase operation K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — — — Word-write to FlexRAM for EEPROM operation — ...
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... K 1.6 M 1. 400 M ≤ 125°C. j Max. Unit Notes — years — years — cycles 2 — years — years — cycles 2 — years — years 3 — writes — writes — writes — writes — writes Freescale Semiconductor, Inc. ...
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... FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • n — data flash cycling endurance (the following graph assumes 10,000 nvmcycd cycles) K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors EEESPLIT × EEESIZE × Write_efficiency × n nvmcycd 35 ...
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... EZP_CK low to EZP_Q output invalid (hold) EP9 EZP_CS negation to EZP_Q tri-state K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 36 Min. Max. Unit 1.71 3.6 V — MHz SYS — MHz SYS — ns EZP_CK 5 — — — — ns — — ns — Freescale Semiconductor, Inc. ...
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... Data and FB_TA input setup FB5 Data and FB_TA input hold 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors EP3 EP2 EP4 EP9 ...
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... Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 38 Min. Max. Unit 1.71 3.6 V — FB_CLK MHz 1/FB_CLK — ns — 13 — ns 13.7 — ns 0.5 — ns Freescale Semiconductor, Inc. Notes ...
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... FB1 FB_CLK FB_A[Y] FB2 FB_D[X] Address FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BEn FB_TA FB_TSIZ[1:0] Figure 11. FlexBus read timing diagram K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB3 FB5 Address FB4 Data AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ 39 ...
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... FB_CSn FB_OEn FB_BEn FB_TA FB_TSIZ[1:0] Figure 12. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 40 FB3 Address Data AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ Freescale Semiconductor, Inc. ...
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... ADCK clock frequency C ADC conversion ≤ 13 bit modes rate rate No ADC hardware averaging Continuous conversions enabled, subsequent conversion time K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 27 and Table 28 Min. Typ. 1. -100 DD ...
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... INPUT PIN = V REFH DDA 1 Min. Typ. 0.215 — Table continues on the next page... 1 Max. Unit Notes 5 461.467 Ksps /C AS SIMPLIFIED CHANNEL SELECT CIRCUIT ADC SAR ENGINE R ADIN R ADIN R ADIN R ADIN C ADIN , REFL SSA 2 Max. Unit Notes 1 Freescale Semiconductor, Inc. AS ...
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... Avg = 32 16-bit single-ended mode • Avg = 32 SFDR Spurious free 16-bit differential mode dynamic range • Avg = 32 16-bit single-ended mode • Avg = 32 K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = REFH DDA REFL 1 Min. Typ. 1.2 2 ...
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... Typ. I × — 1.715 — 719 = V REFH DDA = 2.0 MHz unless otherwise stated. Typical values are for ADCK = V ) (continued) SSA 2 Max. Unit Notes leakage current (refer to the MCU's voltage and current operating ratings) — mV/°C — mV Freescale Semiconductor, Inc. ...
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... R Differential input Gain = PGAD impedance Gain = 16, 32 Gain = 64 R Analog source AS resistance T ADC sampling S time K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 Min. Typ. 1.71 — VREF_OU VREF_OU VREF_OU — SSA V — ...
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... MHz unless otherwise stated. Typical values are for ADCK PGAD Min. Typ. — 420 =1.2V, — 1.54 REFPGA =1.2V, — 0.57 REFPGA Table continues on the next page... Max. Unit Notes 450 Ksps 7 250 Ksps 8 /2 causes drop AS 1 Max. Unit Notes 644 μ — μA — μA Freescale Semiconductor, Inc. ...
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... V Maximum PP,DIFF differential input signal swing SNR Signal-to-noise • Gain=1 ratio • Gain=64 THD Total harmonic • Gain=1 distortion • Gain=64 K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 0.95 1 1.9 2 3.8 4 7.6 8 15.2 16 30.0 31.6 58.8 63.3 — ...
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... Typ. Max. Unit — 3.6 V — 200 μA — 20 μA — — Freescale Semiconductor, Inc. ...
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... Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level LSB = V /64 reference K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1 — — ...
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... Peripheral operating requirements and behaviors 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0.1 0.4 0.7 Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K50 Sub-Family Data Sheet, Rev. 2, 12/2012 1.3 1.6 1.9 2.2 Vin level (V) HYSTCTR S etting 2.5 2.8 3.1 Freescale Semiconductor, Inc. ...
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... Output load capacitance L I Output load current L 1. The DAC reference can be selected small load capacitance (47 pF) can improve the bandwidth performance of the DAC K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1.3 1.6 1.9 2.2 Vin level (V) Min ...
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... Notes 330 μA 1200 μA 200 μ μ μs 1 100 DACR ±8 LSB 2 ±1 LSB 3 ±1 LSB 4 ±0.8 %FSR 5 ±0.6 %FSR — μV/C 6 — %FSR/C 250 Ω V/μs — — -80 dB kHz — — Freescale Semiconductor, Inc. ...
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... Figure 18. Typical INL error vs. digital code K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 53 ...
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... K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 54 Min. 1.71 — — — — — — Table continues on the next page... Typ. Max. Unit — 3 195 μA 465 865 μA ±3 ± — μV/C ±500 — — nA Freescale Semiconductor, Inc. ...
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... Table 35. TRIAMP full range operating requirements Symbol Description V Supply voltage DDA V Input voltage range IN C Output load capacitance L K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. Max. — ±500 — — ±4 — 0 — ...
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... MHz 80 — — dB 0.15 — V -0. — ±0.5 — mA — 20 — — deg — 280 — nV/√Hz — 100 — nV/√Hz Min. Max. 2.4 3.3 V 0.1 V -1.4 V DDA — 100 pf Freescale Semiconductor, Inc. Unit Notes @ 100kHz, High speed mode Unit Notes ...
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... V Voltage reference output — factory trim out V Voltage reference output — user trim out V Voltage reference trim step step K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — ±3 — 4.8 — ±300 — ...
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... Unit — — — — 80 µA — — 360 uA — — µV — 200 — — — 100 — 2 — mV Min. Max. Unit 0 50 °C Min. Max. Unit 1.173 1.225 V Freescale Semiconductor, Inc. Notes µs 1 Notes Notes ...
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... LIM 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. Max. ...
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... DS5 DS6 First data Data Last data Description Table continues on the next page... Max. Unit Notes 3 MHz — / SCK — — — ns — ns — ns DS4 Min. Max. Unit 2.7 3.6 V 12.5 MHz — ns BUS Freescale Semiconductor, Inc. ...
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... Operating voltage Frequency of operation DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time DS3 DSPI_PCSn valid to DSPI_SCK delay K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Description DS10 DS15 DS12 First data Data DS14 ...
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... First data Data Last data Description Max. Unit Notes — 8.5 ns — ns — ns — ns DS4 Min. Max. Unit 1.71 3.6 V — 6.25 MHz — ns BUS (t / SCK SCK/2) — — ns 3.2 — — ns — — Freescale Semiconductor, Inc. ...
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... Normal Run, Wait and Stop mode performance over a limited operating voltage range This section provides the operating performance over a limited operating voltage for the device in Normal Run, Wait and Stop modes. K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DS10 DS15 DS12 ...
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... S10 Min. 2.7 80 45% Table continues on the next page... Max. Unit 3.6 V — ns 55% MCLK period — ns 55% BCLK period 15 ns — — ns — ns — S10 S8 Max. Unit 3.6 V — ns 55% MCLK period Freescale Semiconductor, Inc. ...
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... This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 51. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Operating voltage Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 4.5 2 — — ...
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... S10 Min. 1.71 80 45% Table continues on the next page... K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Max. Unit — ns 55% MCLK period — ns 55% BCLK period 15 ns — — ns — ns — S10 S8 Max. Unit 3.6 V — ns 55% MCLK period Freescale Semiconductor, Inc. ...
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... This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 53. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Operating voltage Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 5.8 2 — — ...
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... S10 Min. 1.71 250 45% Table continues on the next page... K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Max. Unit — ns 55% MCLK period — ns 55% BCLK period 45 ns — — ns — ns — S10 S8 Max. Unit 3.6 V — ns 55% MCLK period Freescale Semiconductor, Inc. ...
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... Table 55. TSI electrical specifications Symbol Description V Operating voltage DDTSI C Target electrode capacitance range ELE f Reference oscillator frequency REFmax f Electrode oscillator frequency ELEmax Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min — — S11 S12 S13 S15 S19 ...
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... I )/( NSCN) ref ext ref = 16 μA (REFCHRG = 7 1.0 pF ref ref = 32 μA (REFCHRG = 15 0.5 pF ref ref Unit Notes μ μ fF/count 8 fF/count 9 fF/count 10 fF/count 11 bits μs 12 μA μA 13 Freescale Semiconductor, Inc. ...
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... ADC1_DM3 ADC1_DM3 13 PGA1_DP/ PGA1_DP/ PGA1_DP/ ADC1_DP0/ ADC1_DP0/ ADC1_DP0/ ADC0_DP3 ADC0_DP3 ADC0_DP3 K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. www.freescale.com and perform a keyword search for Then use this document number 98ASS23174W ALT1 ALT2 ALT3 ALT4 Pinout ALT5 ALT6 ALT7 EzPort ...
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... OP1_DP5 OP1_DP5 OP1_DP5 30 XTAL32 XTAL32 XTAL32 31 EXTAL32 EXTAL32 EXTAL32 32 VBAT VBAT VBAT 33 PTA0 JTAG_TCLK/ TSI0_CH1 SWD_CLK/ EZP_CLK K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 72 ALT1 ALT2 ALT3 ALT4 PTA0 UART0_CTS_ FTM0_CH5 b/ UART0_COL_b ALT5 ALT6 ALT7 EzPort JTAG_TCLK/ EZP_CLK SWD_CLK Freescale Semiconductor, Inc. ...
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... CMP1_IN0/ CMP1_IN0/ TSI0_CH15 TSI0_CH15 58 PTC3/ CMP1_IN1 CMP1_IN1 LLWU_P7 59 VSS VSS VSS 60 VDD VDD VDD K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTA1 UART0_RX FTM0_CH6 PTA2 UART0_TX FTM0_CH7 PTA3 UART0_RTS_b FTM0_CH0 PTA4/ FTM0_CH1 LLWU_P3 PTA18 FTM0_FLT2 ...
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... LLWU_P15 PTD7 CMT_IRO UART0_TX FTM0_CH7 ALT5 ALT6 ALT7 EzPort FB_AD11 CMP1_OUT FB_AD10 CMP0_OUT I2S0_MCLK FB_AD8 FB_AD7 FTM2_FLT0 FB_AD5 FB_RW_b FB_CS5_b/ FB_TSIZ1/ FB_BE23_16_b FB_CS4_b/ FB_TSIZ0/ FB_BE31_24_b FB_ALE/ FB_CS1_b/ FB_TS_b FB_CS0_b FB_AD4 FB_AD3 FB_AD2 EWM_IN FB_AD1 EWM_OUT_b FB_AD0 FTM0_FLT0 FTM0_FLT1 Freescale Semiconductor, Inc. ...
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... PGA0_DP/ADC0_DP0/ADC1_DP3 PGA0_DM/ADC0_DM0/ADC1_DM3 PGA1_DP/ADC1_DP0/ADC0_DP3 PGA1_DM/ADC1_DM0/ADC0_DM3 VDDA VREFH VREFL VSSA ADC1_SE16/OP1_OUT/CMP2_IN2/ADC0_SE22/OP0_DP2/OP1_DP2 ADC0_SE16/OP0_OUT/CMP1_IN2/ADC0_SE21/OP0_DP1/OP1_DP1 Figure 30. K50 80 LQFP Pinout Diagram 9 Revision History The following table provides a revision history for this document. K50 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc ...
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... Revision History Rev. No. Date Substantial Changes 1 6/2012 Initial public revision 2 12/2012 Replaced TBDs throughout. K50 Sub-Family Data Sheet, Rev. 2, 12/2012. 76 Table 56. Revision History Freescale Semiconductor, Inc. ...
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... Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time ...