P3041NXE1NNB Freescale Semiconductor, P3041NXE1NNB Datasheet - Page 2

• Manufacturer Part Number: P3041NXE1NNB
• Description: Microprocessors - MPU P3041 Qual ext temp w/ SEC 1333 rev 1.1
• Manufacturer: Freescale Semiconductor

Specifications of P3041NXE1NNB

• Rohs: yes
• Processor Series: P3041
• Core: e500mc
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1.5 GHz
• Program Memory Size: 1 MB
• Interface Type: USB
• Mounting Style: SMD/SMT
• Package / Case: FCPBGA-1295

Key Architectural Features
• Three-level cache hierarchy: The low-
• Hardware hypervisor: The e500mc supports
• DPAA: This offloads the cores from the
• CoreNet switch fabric: The fabric-based
latency 32 KB L1 instruction and data
caches are augmented by a unified 128
KB private backside L2 cache per core.
The L2 is 8-way set associative and is ECC
protected. When instructions are locked in
the L2, the per-packet “hot” code is always
readily available, improving application
performance. A shared 1 MB CoreNet
platform cache (L3) facilitates core-to-core
communications and minimizes accesses to
main memory.
a hardware hypervisor that is designed to
enable each core to run its own operating
system completely independent of the other
core. The hypervisor facilitates resource
sharing and partitioning in a multicore
environment, and provides protection in
the event that a core, driven by malicious
or improperly programmed code, tries to
access memory it does not have permission
to read or write. It also allows the sharing and
partitioning of various I/Os across the cores
and it helps ensure that incoming memory
mapped transactions are written only into
appropriate ranges of the memory map.
need to perform routine packet-handling
tasks. For instance, the DPAA will extract
headers from incoming packets, police
them, classify them and manage their data
buffers. The work is assigned to cores
with a three-level scheduling hierarchy,
which can also facilitate sharing of packet
workload over multiple cores.
interface provides scalable on-chip, point-
to-point connectivity supporting concurrent
traffic to and from multiple resources
connected to the fabric, eliminating single-
point bottlenecks for non-competing
resources. This is designed to eliminate bus
contention and latency issues associated
with scaling shared bus architectures that
are common in other multicore approaches.
To learn more about Freescale QorIQ communications
platforms, please visit
Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet is a
trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power
Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks
licensed by Power.org. © 2011 Freescale Semiconductor, Inc.
Document Number: QP3041FS REV 3
Target Applications
The P3 family is targeted at mixed control
plane and data plane applications, where in
previous generations separate devices would
implement each function. Typically, one or
two cores would implement the control plane,
while the remaining cores implement the data
plane. The hardware hypervisor facilitates this,
with its capability to safely provision flexible
core allocations into groups running SMP, one
core running alone, separate cores running in
parallel or a core running end-user applications.
There are many applications that look similar to
this, including:
• Integrated access router (IAD): Dual SATA
• Base station network interface card (NIC):
Features
Four e500mc cores, built on
Power Architecture technology
• Up to 1.5 GHz
• Each with 128 KB backside L2 cache
Memory controller
• DDR3, 3L up to 1.3 GHz
• 32/64-bit data bus with ECC
High-speed interconnects
• 18x 5 GHz SerDes lanes
• 4x PCI Express
• 2x Serial RapidIO 1.3/2.1 controllers at up
ports provide high-speed, cost-effective
storage options for statistics or large
databases. Compared to SGMII, 2.5
Gbps Ethernet enables the next step in
performance connectivity to switches.
Dual Serial RapidIO
can be used for redundancy or multiple
connections, both to the backplane or
to the DSP farm. With improved Type 11
messaging and new support for Type 9 data
streaming, the Serial RapidIO interconnect
can now be used not only as a control plane
interface, but can also achieve its intended
potential as a highly efficient data path.
5 GHz
to 5 GHz
®
2.0 controllers at up to
®
ports (up to 5 GHz)
freescale.com/QorIQ
• 2x SATA 2.0 at 3 Gbps
• 2x USB 2.0 with PHY
CoreNet switch fabric
• 1 MB shared CoreNet platform cache (L3)
Ethernet
• 5x 10/100/1000 Ethernet controller
• 1x 10 Gigabit Ethernet controllers
• All with classification, hardware queueing,
• Up to 1x XAUI, 4x SGMII or 2.5 Gbps
Data path acceleration
• SEC 4.2: public key accelerator, DES,
• PME 2.1: searches for 128 byte text strings
• RapidIO messaging: Type 9 and 11
Device
• 45 nm SOI process technology
• 1295-pin FCPBGA package, 37.5 mm x
Enablement
• Enea
• Green Hills
• Mentor Graphics
• CodeSourcery: Tool chain support for new
• WindRiver
• Development system: Four PCI Express
with ECC
policing, buffer management, checksum
offload, QoS, lossless flow control,
IEEE
SGMII, 2x RGMII
AES, message digest accelerator, random
number generator, ARC4, SNOW 3G F8
and F9, CRC, Kasumi
in 32 KB patterns in 128M sessions
37.5 mm
and hardware development tools, trace
tools and real-time operating systems
Linux
core technology
slots, one Serial RapidIO slot, one XAUI
slot, one SGMII slot, SATA disk, Aurora
debug port
®
®
®
: Real-time operating system support
1588
solution
®
®
: Simics
: Complete portfolio of software
®
: Commercial grade
®
model