MPC8308CZQADDA Freescale Semiconductor, MPC8308CZQADDA Datasheet - Page 77

• Manufacturer Part Number: MPC8308CZQADDA
• Description: Microprocessors - MPU E300 ext tmp Qual266
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308CZQADDA

• Processor Series: MPC8308
• Core: e300
• Maximum Clock Frequency: 266 MHz
• Interface Type: I2C, JTAG, UART
• Operating Supply Voltage: 0.95 V to 1.05 V
• Maximum Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-474

23 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
device
23.1
The device includes two PLLs.
23.2
Each of the PLLs listed above is provided with power through independent power supply pins (AV
core PLL and AV
preferably these voltages are derived directly from V
following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs’ resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
This figure shows the PLL power supply filter circuits.
Freescale Semiconductor
1. The platform PLL generates the platform clock from the externally supplied SYS_CLK_IN input.
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL
ratio configuration bits as described in
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in
System Clocking
PLL Power Supply Filtering
DD2
V
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
DD
for the platform PLL). The AV
Figure 54. PLL Power Supply Filter Circuit
10
2.2 µF
Section 21.3, “Core PLL Configuration.”
Section 21.2, “System PLL Configuration.”
Figure
DD
DD
Low ESL Surface Mount Capacitors
level should always be equivalent to V
through a low pass filter scheme such as the
2.2 µF
54, one to each of the two AV
DD
AV
DD1
pin being supplied to minimize
and AV
DD2
System Design Information
DD
pins. By
DD
DD1
, and
for
DD
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