DR-WLS1273L-102 RFM, DR-WLS1273L-102 Datasheet - Page 7

• Manufacturer Part Number: DR-WLS1273L-102
• Description: WiFi / 802.11 Modules 2.4 and 5.8GHz + BT
• Manufacturer: RFM

Specifications of DR-WLS1273L-102

• Rohs: yes
• Protocol Supported: 802.11 a/b/g
• Frequency Band: 64 kHz to 4 GHz
• Data Rate: 1 Mbps, 2 Mbps, 5.5 Mbps, 11 Mbps
• Interface Type: SDIO, UART
• Operating Supply Voltage: 3 V to 4.2 V
• Supply Current Transmitting: 350 mA
• Supply Current Receiving: 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Modulation Technique: CCK, DSSS

BT Audio CODEC Interface
The CODEC interface is a fully dedicated programmable serial port that provides the logic to interface to
several kinds of PCM codecs. The interface supports:
• Two voice channels
• Master/slave modes
• Coding schemes: μ-Law, A-Law, Linear, Transparent
• Long & short frames
• Different data lengths, orders and positions
• UDI profile
• High rate PCM interface for EDR
• Enlarged interface options to support a wider variety of codecs
• PCM bus sharing
PCM Hardware Interface
The PCM interface is one implementation of the codec interface. It contains the following four lines:
• Clock - configurable direction (input or output)
• Frame Sync - configurable direction (input or output)
• Data In - Input
• Data Out - Output/Hi-Z
The DR-WLS1273L-102 device can be either the master of the interface where it generates the clock and
the frame-sync signals, or slave where it receives these two signals. The PCM interface is fully configured
by means of a VS command. For slave mode, clock input frequencies of up to 16 MHz are supported. At
clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the DR-WLS1273L-
102 can generate any clock frequency between 64 kHz and 4.096 MHz.
Data Format
The data format is fully configurable:
• The data length can be from 8 to 320 bits, in 1-bit increments, when working with two channels, or up to
640 bits when using 1 channel. The data length can be set independently for each channel.
• The data position within a frame is also configurable with 1-clock (bit) resolution, and can be set inde-
pendently (relative to the edge of the Frame Sync signal) for each channel.
• The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start
with MSB while Data_Out starts with LSB. Each channel is separately configurable. The inverse bit order
(i.e. LSB first) is supported only for sample sizes up to 24 bits.
• The data in and data out size do not necessarily have to be the same length.
• The Data_Out line is configured as a ‘high-Z’ output between data words. Data_Out can also be set for
permanent high-Z, irrespective of data out. This allows the DR-WLS1273L-102 to be a bus slave in a mul-
ti-slave PCM environment. At power up, Data_Out is configured as high-Z.
Frame-Idle Period
The CODEC interface has the capability for frame-idle periods, where the PCM clock can “take a break”
and become ‘0’ at the end of the PCM frame, after all data has been transferred. The DR-WLS1273L-102
supports frame-idle periods both as master and slave of the PCM bus. When DR-WLS1273L-102 is the
master of the interface, the frame-idle period is configurable. There are 2 configurable parameters:
• Clk_Idle_Start - indicates the number of PCM clock cycles from the beginning of the frame till the begin-
ning of the idle period. After Clk_Idle_Start clock cycles, the clock becomes ‘0’.
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DR-WLS1273L-102 Data Sheet - 12/13/12