74FCT162511CTPAG8 IDT, 74FCT162511CTPAG8 Datasheet - Page 3

• Manufacturer Part Number: 74FCT162511CTPAG8
• Description: Bus Transceivers
• Manufacturer: IDT

Specifications of 74FCT162511CTPAG8

• Rohs: yes
• Part # Aliases: IDT74FCT162511CTPAG8

PIN CONFIGURATION
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
OEAB
OEBA
PERA
LEAB
LEBA
GND
GND
GND
PA
V
V
PA
A
A
A
A
A
A
A
A
CC
A
A
A
A
A
A
A
A
CC
10
11
12
13
14
15
1
2
0
1
2
3
4
5
6
7
8
9
SSOP/ TSSOP/ CERPACK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TOP VIEW
48
43
56
55
54
53
52
51
50
49
47
46
45
44
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GEN/CHK
CLKAB
PB
GND
PERB
GND
GND
PB
CLKBA
ODD/EVEN
B
B
V
B
B
B
B
B
B
B
B
B
B
B
B
V
B
B
CC
10
11
12
13
CC
14
15
0
1
2
3
4
5
6
7
8
9
1
2
3
CAPACITANCE
PIN DESCRIPTION
NOTE:
1. The PAx pin input is internally disabled during parity generation. This means that when
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
C
Symbol
C
C
Symbol
V
V
T
I
OUT
Pin Names
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
A x
B x
PERA
PERB
PAx
PBx
ODD/EVEN
GEN/CHK
generating parity in the A to B direction there is no need to add a pull up resistor to
guarantee state. The pin will still function properly as the parity output for the B to A
direction.
TERM
TERM
STG
IN
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
I/O
O
(1)
(2)
(3)
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
Input Capacitance
I/O Capacitance
Open Drain
Capacitance
Parameter
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
Parity Error (Open Drain) on A Outputs
Parity Error (Open Drain) on B Outputs
A-to-B Parity Input, B-to-A Parity Output
B-to-A Parity Input, A-to-B Parity Output
Parity Mode Selection Input
A to B Port Generate or Check Mode Input
Description
(1)
(T
A
= +25°C, F = 1.0MHz)
Description
Conditions
V
V
V
OUT
OUT
IN
= 0V
= 0V
= 0V
–0.5 to V
Typ.
3.5
3.5
3.5
–65 to +150
–60 to +120
–0.5 to 7
Max
CC
Max.
+0.5
6
8
6
(1)
(1)
(1)
(1)
(1)
Unit
Unit
pF
pF
pF
mA
° C
V
V