MAX5581AEUP-T Maxim Integrated, MAX5581AEUP-T Datasheet - Page 26

• Manufacturer Part Number: MAX5581AEUP-T
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5581AEUP-T

• Number Of Converters: 4
• Number Of Dac Outputs: 4
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Settling Time: 6 us
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP EP
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 2.7 V
• Voltage Reference: External

Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Settling-Time-Mode Write Example:
To configure DACA and DACD into FAST mode and
DACB and DACC into SLOW mode, use the command
in Table 12.
To read back the settling-time-mode bits, use the com-
mand in Table 13.
The
MAX5580–MAX5585 are defined the same as the CPOL
and CPHA bits in the SPI standard. Set the DAC’s
CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or
CPOL = 1 and CPHA = 1 for MICROWIRE and SPI
applications requiring the clocking of data in on the ris-
Table 12. Settling-Time-Mode Write Example
X = Don’t care.
Table 13. Settling-Time-Mode Read Command
X = Don’t care.
Table 14. CPOL and CPHA Bits
Table 15. CPOL and CPHA Write Command
X = Don’t care.
Table 16. CPOL and CPHA Read Command
X = Don’t care.
26
D OU TRB
D OU TRB
DATA
DATA
DATA
DATA
DIN
DIN
DIN
DIN
CPOL
______________________________________________________________________________________
0
0
1
1
CPOL
1
1
1
X
1
X
and
CPHA
1
1
X
1
X
1
0
1
0
1
CPHA
1
1
CPOL and CPHA Control Bits
X
1
X
1
CONTROL BITS
CONTROL BITS
Default values at power-up when DSP is connected to DV
of SCLK.
Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge
of SCLK.
Data is clocked in on the falling edge of SCLK.
Data is clocked in on the rising edge of SCLK.
CONTROL BITS
CONTROL BITS
1
0
control
X
1
0
X
0
1
0
X
1
X
bits
0
1
0
X
X
1
of
0
0
0
X
1
X
the
0
X
X
1
1
X
ing edge of SCLK. Set the DAC’s CPOL and CPHA bits
to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA =
0 for DSP and SPI applications, requiring the clocking
of data in on the falling edge of SCLK (refer to the
Programmer’s Handbook and see Table 14 for details).
At power-up, if DSP = DV
is zero and if DSP = DGND, the default value of CPHA
is one. The default value of CPOL is zero at power-up.
To write to the CPOL and CPHA bits, use the command
in Table 15.
To read back the device’s CPOL and CPHA bits, use
the command in Table 16.
X
X
DESCRIPTION
X
X
X
X
X
X
X
X
X
X
DD
X
X
X
X
X
X
. Data is clocked in on the rising edge
DATA BITS
DATA BITS
DATA BITS
DATA BITS
X
X
X
X
X
X
DD
, the default value of CPHA
S P D D S P D C S P D B S P D A
X
X
X
1
X
X
X
X
0
X
C P O L C P H A
C P O L C P H A
X
X
0
X
X
1