AT24C16C-STUM-T Atmel, AT24C16C-STUM-T Datasheet - Page 6

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AT24C16C-STUM-T

Manufacturer Part Number
AT24C16C-STUM-T
Description
EEPROM SERIAL EEPROM 16K (2K X 8) 2-WIRE 1.7V
Manufacturer
Atmel
Datasheet

Specifications of AT24C16C-STUM-T

Rohs
yes
Memory Size
16 K
Organization
2048 x 8
Data Retention
100 yr
Maximum Clock Frequency
1000 kHz
Maximum Operating Current
3 mA
Operating Supply Voltage
1.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOT-23
Interface Type
2-Wire Serial
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
5000
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.7 V
3.
6
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see <blue>Figure 3-4 on page 7). Data changes during SCL
high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see <blue>Figure 3-5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (see <blue>Figure 3-5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
STANDBY MODE: The Atmel
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.
2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be
protocol reset by following these steps:
Figure 3-1.
1. Create a start bit condition
2. Clock nine cycles
3. Create another start bit followed by stop bit condition as shown below
Atmel AT24C16C
SDA
SCL
Software Reset
Start bit
®
1
AT24C16C features a low-power standby mode which is enabled:
2
Dummy Clock Cycles
3
8
9
Start bit
8719A–SEEPR–9/10
Stop bit

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