M95160-FDW6TP STMicroelectronics, M95160-FDW6TP Datasheet - Page 23

• Manufacturer Part Number: M95160-FDW6TP
• Description: EEPROM 16Kbit SPI EEPROM 2.5 to 5.5V 10 MHz
• Manufacturer: STMicroelectronics

Specifications of M95160-FDW6TP

• Product Category: EEPROM
• Rohs: yes

M95160 M95160-W M95160-R M95160-F
Figure 13. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in
Note:
S
C
D
Q
In the case of
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
The self-timed write cycle t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
if a Write cycle is already in progress,
if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
0
1
High Impedance
Figure
2
Instruction
3
4
13, Chip Select (S) is driven high after the eighth bit of the data byte
5
Table
W
6
is internally executed as a sequence of two consecutive
Doc ID 022580 Rev 3
7
15
4, the most significant address bits are Don’t Care.
8
14 13
9 10
16-Bit Address
3
20 21 22 23 24 25 26 27
2
1
0
7
6
5
Data Byte
4
3
28 29 30
Figure
2
1
14, the next byte
0
31
Instructions
AI01795D
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