M24C32-DFDW6TP STMicroelectronics, M24C32-DFDW6TP Datasheet - Page 16
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M24C32-DFDW6TP
Manufacturer Part Number
M24C32-DFDW6TP
Description
EEPROM 32 Kbit I2C EEProm 4kB 2.5V to 5.5V
Manufacturer
STMicroelectronics
Datasheet
1.M24C32-FDW6TP.pdf
(40 pages)
Specifications of M24C32-DFDW6TP
Rohs
yes
Available stocks
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Quantity
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Instructions
5.1.2
16/40
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, b16-b5, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 7.
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write (cont'd)
Figure
Write mode sequences with WC = 1 (data write inhibited)
7. After each transferred byte, the internal page address counter is
NO ACK
Dev sel
Dev sel
Data in N
Doc ID 4578 Rev 21
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
R/W
R/W
ACK
ACK
NO ACK
Byte addr
Byte addr
ACK
ACK
Byte addr
Byte addr
ACK
ACK
Data in 1
Data in
NO ACK
NO ACK
Data in 2
AI01120d