ATAES132-MA3H-ER-T Atmel, ATAES132-MA3H-ER-T Datasheet - Page 139
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ATAES132-MA3H-ER-T
Manufacturer Part Number
ATAES132-MA3H-ER-T
Description
EEPROM AES 32Kbit (MA3) I2C
Manufacturer
Atmel
Datasheet
1.ATAES132-SH-EQ.pdf
(166 pages)
Specifications of ATAES132-MA3H-ER-T
Rohs
yes
Maximum Clock Frequency
1 MHz
Operating Supply Voltage
6 V
Maximum Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
UDFN-8
Interface Type
I2C
Factory Pack Quantity
5000
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L.2.
L.2.1.
L.2.2.
L.2.3.
Power State Transitions
Power Up is a transition from the Off State to one of the three powered states. Power Down is the transition from a powered
state to the Off State. Wakeup is the transition from one of the two low power states to the Active State.
Power Up
Power up begins when the power supply is turned on, causing the V
voltage. Power up occurs in three stages.
During the power up process, the device is unable to accept commands. In the SPI interface mode, the device is ready to
receive a read status register command after the power up time t
time required to complete the power up process. In the I
completion of power up (time t
The last stage of the power up procedure is to enter the active, standby, or sleep state specified by bit 6 and 7 of the
ChipConfig register. The ChipState register is set to 0xFFFF at power up. (see Section L.3)
Table L-40. Coding of the ChipConfig.PowerUpState bits in the ChipConfig register
During power up, the SPI chip select should follow the V
with a pull-up resistor if the ATAES132 is configured in the SPI interface mode. The ATAES132 does not support hot
swapping or hot plugging. Connecting or disconnecting this device to a system while power is energized can cause
permanent damage to the ATAES132.
Power Down
Before power down, the device must be deselected (if configured for SPI) and placed in the active, standby, or sleep state.
During power down, the SPI chip select should be allowed to follow the V
interface mode.
The ATAES132 should not be powered down when the WIP status bit indicates that an EEPROM write or cryptographic
operation is in progress. If the WIP status bit is 0b, then it is safe to power down the device.
Entering the Standby State
If the ATAES132 is in the active state, the host can send a sleep command to place the ATAES132 in the standby state. (See
Section 7.24) It is not possible to transition the device directly from the sleep state to the standby state. The host must
wakeup the device and then must send a sleep command to place the device in standby.
The device can also be configured to enter the standby state at power up as described in Section L.2.1.
The ATAES132 exits standby state only if a wakeup event occurs on the IO pins. Wakeup is discussed in Sections L.2.5 and
L.2.6. The ChipState register does not change when the ATAES132 enters or leaves the standby state. (see Section L.3)
1.
5.
6.
Bit 7
First stage
The voltage regulator and other analog circuitry are activated
Second stage
Third stage
The serial interface logic is activated so that the ATAES132 can report the device status to the host
The ATAES132 enters the power state specified by the ChipConfig register
1
1
0
0
Bit 6
1
0
1
0
PU.RDY
Description
Device goes to the Active State at Power Up
Device goes to the Standby State at Power Up
Device goes to the Sleep State at Power Up
).
2
CC
C interface mode, the device will NAK all instructions prior to the
voltage. It is recommended that the
PU.STATUS
CC
voltage to rise continuously from V
Atmel ATAES132 Preliminary Datasheet
CC
. The power up ready time of t
voltage if the ATAES132 is configured in SPI
pin be connected to V
8760A−CRYPTO−5/11
PU.RDY
SS
to the operating
specifies the
CC
139
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