93LC86C-I/PG Microchip Technology, 93LC86C-I/PG Datasheet - Page 5

• Manufacturer Part Number: 93LC86C-I/PG
• Description: EEPROM 1024x16-2048x8 Lead Free Package
• Manufacturer: Microchip Technology

Specifications of 93LC86C-I/PG

• Product Category: EEPROM
• Rohs: yes
• Memory Size: 16 Kbit
• Organization: 256 x 8
• Data Retention: 200 yr
• Maximum Clock Frequency: 3 MHz
• Maximum Operating Current: 3 mA
• Operating Supply Voltage: 2.5 V, 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Interface Type: Microwire
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.5 V

2.0
When the ORG* pin is connected to V
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
BUSY status during a programming operation. The
READY/BUSY status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the HIGH-Z
state on the falling edge of CS.
2.1
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL or WRAL). As soon as CS is high, the device is
no longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
 2004 Microchip Technology Inc.
FUNCTIONAL DESCRIPTION
Start Condition
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
CC
, the (x16)
2.2
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of the
driver, the higher the voltage at the Data Out pin. In
order to limit this current, a resistor should be con-
nected between DI and DO.
2.3
All modes of operation are inhibited when V
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
ORG*
DI
CLK
Note:
CS
PE*
*ORG and PE inputs are not available on
A/B devices.
Data In/Data Out (DI/DO)
Data Protection
Data Register
V
For added protection, an EWDS command
should be performed after every write
operation.
CC
Memory
Register
Array
Decode
Clock
Mode
Logic
V
SS
Address
Decoder
Address
Counter
DS21797D-page 5
Output
Buffer
CC
is below
DO