MAX3395EEBC+T Maxim Integrated Products, MAX3395EEBC+T Datasheet - Page 7

• Manufacturer Part Number: MAX3395EEBC+T
• Description: IC LVL XLTR LV 6MBPS 12-UCSP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3395EEBC+T

• Logic Function: Translator, Bidirectional, 3-State
• Number Of Bits: 4
• Input Type: Logic
• Output Type: Logic
• Data Rate: 6Mbps
• Number Of Channels: 4
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 50ns
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 12-UCSP®
• Supply Voltage: 1.65 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
The MAX3394E/MAX3395E/MAX3396E bidirectional
level translators provide level shifting required for data
transfer in a multivoltage system. Internal slew-rate
enhancement circuitry features 10mA current-sink and
15mA current-source drivers to isolate capacitive loads
from lower current drivers. In open-drain systems, slew-
rate enhancement enables fast data rates with larger
TDFN
EP
—
—
—
—
—
—
—
—
—
—
—
—
1
2
3
4
5
6
7
8
MAX3394E
UCSP
Octal-Level Translators with Speed-Up Circuitry
C3
C2
C1
A1
B1
A2
A3
B3
—
—
—
—
—
—
—
—
—
—
—
—
—
_______________________________________________________________________________________
TQFN
Detailed Description
11
10
12
EP
—
—
—
—
—
—
—
—
6
9
5
2
1
3
4
7
8
MAX3395E
PIN
UCSP
B1
B3
C1
C2
B4
A2
A1
B2
A3
A4
C4
C3
—
—
—
—
—
—
—
—
—
TQFN
EP
14
18
16
13
20
19
15
17
12
11
10
4
3
1
2
9
5
6
7
8
MAX3396E
UCSP
D3
C1
D1
D4
D2
C2
C3
D5
C4
C5
A4
A1
B1
A3
B2
A2
B3
A5
B4
B5
—
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
pullup resistors and increased bus load capacitance.
Externally applied voltages, V
high levels for the device. A logic-low signal on one I/O
side of the device appears as a logic-low signal on the
opposite I/O side and vice-versa. Each I/O line is pulled
up to V
the devices to be driven by either push-pull or open-
drain drivers.
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
NAME
GND
V
EN
EP
V
CC
L
CC
CC
CC
CC
CC
CC
CC
CC
L
L
L
L
L
L
L
L
2
1
3
4
5
6
7
8
1
2
4
3
5
6
7
8
CC
V
V
1µF or greater ceramic capacitor as close to the
device as possible.
Enable Input. Drive EN logic high for normal
operation. Drive EN logic low to force all I/O lines to
a high-impedance state and disconnect internal
pullup resistors.
I/O 1 Referred to V
I/O 2 Referred to V
Ground
I/O 2 Referred to V
I/O 1 Referred to V
Logic Supply Voltage +1.2V ≤ V
to GND with a 0.1µF or greater ceramic capacitor
as close to the device as possible.
I/O 3 Referred to V
I/O 4 Referred to V
I/O 4 Referred to V
I/O 3 Referred to V
I/O 5 Referred to V
I/O 6 Referred to V
I/O 7 Referred to V
I/O 8 Referred to V
I/O 5 Referred to V
I/O 6 Referred to V
I/O 7 Referred to V
I/O 8 Referred to V
Exposed Pad. Connect exposed pad to GND.
CC
CC
or V
Supply Voltage +1.65V ≤ V
to GND with a 0.1µF ceramic capacitor and a
L
by an internal pullup resistor, allowing
CC
CC
L
L
L
L
CC
CC
CC
CC
CC
CC
L
L
L
L
FUNCTION
CC
Pin Description
and V
CC
L
≤ V
L
≤ +5.5V. Bypass
, set the logic-
CC
. Bypass V
L
7