LFE3-95EA-9FN484I Lattice, LFE3-95EA-9FN484I Datasheet - Page 21
LFE3-95EA-9FN484I
Manufacturer Part Number
LFE3-95EA-9FN484I
Description
FPGA - Field Programmable Gate Array 92K LUTs 133 I/O 1.2V -9 SPEED
Manufacturer
Lattice
Datasheet
1.LFE3-95EA-7LFN672I.pdf
(141 pages)
Specifications of LFE3-95EA-9FN484I
Rohs
yes
Number Of Gates
92 K
Number Of Logic Blocks
240
Embedded Block Ram - Ebr
4420 Kbit
Number Of I/os
133
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-484
Distributed Ram
188 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
230.7 mA
Factory Pack Quantity
60
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-95EA-9FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-20. Sources of Edge Clock (Left and Right Edges)
Figure 2-21. Sources of Edge Clock (Top Edge)
The edge clocks have low injection delay and low skew. They are used to clock the I/O registers and thus are ideal
for creating I/O interfaces with a single clock signal and a wide data bus. They are also used for DDR Memory or
Generic DDR interfaces.
from DLL Slave Delay
from DLL Slave Delay
Top Right PLL_CLKOS
Top Right PLL_CLKOP
Top Left PLL_CLKOS
DLL Output CLKOP
PLL Output CLKOS
PLL Output CLKOP
DLL Output CLKOS
PLL Output CLKOP
PLL Output CLKOS
Top left PLL_CLKOP
Right DLL_CLKOS
Right DLL_CLKOP
Left DLL_CLKOP
Left DLL_CLKOS
(Right DLL_DEL)
PLL Input Pad
PLL Input Pad
(Left DLL_DEL)
CLKINDEL
CLKINDEL
Input Pad
Input Pad
CLKINDEL
CLKINDEL
Input Pad
Input Pad
Routing
Routing
Routing
Routing
2-18
7:1
7:1
7:1
7:1
Left and Right
Left and Right
Edge Clocks
Edge Clocks
ECLK1
ECLK2
ECLK1
ECLK2
LatticeECP3 Family Data Sheet
Architecture
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