LFE3-35EA-7LFN484C Lattice, LFE3-35EA-7LFN484C Datasheet - Page 28
LFE3-35EA-7LFN484C
Manufacturer Part Number
LFE3-35EA-7LFN484C
Description
FPGA - Field Programmable Gate Array 33.3K LUTs 295 I/O 1.2V -7 SPEED
Manufacturer
Lattice
Datasheet
1.LFE3-95EA-7LFN672I.pdf
(141 pages)
Specifications of LFE3-35EA-7LFN484C
Rohs
yes
Number Of Gates
33 K
Number Of Logic Blocks
72
Embedded Block Ram - Ebr
1327 Kbit
Number Of I/os
295
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-484
Distributed Ram
68 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
53.7 mA
Factory Pack Quantity
60
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-35EA-7LFN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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MAC DSP Element
In this case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated
value. This accumulated value is available at the output. The user can enable the input and pipeline registers, but
the output register is always enabled. The output register is used to store the accumulated value. The ALU is con-
figured as the accumulator in the sysDSP slice in the LatticeECP3 family can be initialized dynamically. A regis-
tered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-27
shows the MAC sysDSP element.
Figure 2-27. MAC DSP Element
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
I
C
IR
AA
MULTA
OR
PR
AMUX
A_ALU
IR
From FPGA Core
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-25
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
LatticeECP3 Family Data Sheet
PR
OR
IR
BB
IR
COUT
SROB
SROA
DSP Slice
Next
Architecture
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