LFE3-35EA-7LFN672C Lattice, LFE3-35EA-7LFN672C Datasheet - Page 117
LFE3-35EA-7LFN672C
Manufacturer Part Number
LFE3-35EA-7LFN672C
Description
FPGA - Field Programmable Gate Array 33.3K LUTs 310 I/O 1.2V -7 SPEED
Manufacturer
Lattice
Datasheet
1.LFE3-95EA-7LFN672I.pdf
(141 pages)
Specifications of LFE3-35EA-7LFN672C
Rohs
yes
Number Of Gates
33 K
Number Of Logic Blocks
72
Embedded Block Ram - Ebr
1327 Kbit
Number Of I/os
310
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-672
Distributed Ram
68 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
53.7 mA
Factory Pack Quantity
40
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-35EA-7LFN672C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Signal Descriptions (Cont.)
D7/SPID0
DI/CSSPI0N/CEN
Dedicated SERDES Signals
PCS[Index]_HDINNm
PCS[Index]_HDOUTNm
PCS[Index]_REFCLKN
PCS[Index]_HDINPm
PCS[Index]_HDOUTPm
PCS[Index]_REFCLKP
PCS[Index]_VCCOBm
PCS[Index]_VCCIBm
1. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage,
2. These pins are dedicated inputs or can be used as general purpose I/O.
3. m defines the associated channel in the quad.
care must be given.
Signal Name
3
I/O
I/O
I/O
—
—
O
O
I
I
I
I
Parallel configuration I/O. SPI/SPIm data input. Open drain during configura-
tion.
Serial data input for slave serial mode. SPI/SPIm mode chip select.
High-speed input, negative channel m
High-speed output, negative channel m
Negative Reference Clock Input
High-speed input, positive channel m
High-speed output, positive channel m
Positive Reference Clock Input
Output buffer power supply, channel m (1.2V/1.5)
Input buffer power supply, channel m (1.2V/1.5V)
4-3
Description
LatticeECP3 Family Data Sheet
Pinout Information
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