LCMXO2-4000HE-6MG184I Lattice, LCMXO2-4000HE-6MG184I Datasheet - Page 29
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LCMXO2-4000HE-6MG184I
Manufacturer Part Number
LCMXO2-4000HE-6MG184I
Description
FPGA - Field Programmable Gate Array 4320 LUTs, 151 I/O 1.2V, -6 Speed, IND
Manufacturer
Lattice
Series
MachXO2r
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000HE-6MG184I
Rohs
yes
Number Of Logic Blocks
4320
Embedded Block Ram - Ebr
92 Kbit
Number Of I/os
150
Maximum Operating Frequency
388 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Package / Case
BGA-184
Distributed Ram
34 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
124 uA
User Flash Memory - Ufm
96 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000HE-6MG184I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Table 2-13. Supported Output Standards
sysIO Buffer Banks
The numbers of banks vary between the devices of this family. MachXO2-1200U, MachXO2-2000/U and higher
density devices have six I/O banks (one bank on the top, right and bottom side and three banks on the left side).
The MachXO2-1200 and lower density devices have four banks (one bank per side). Figures 2-18 and 2-19 show
the sysIO banks and their associated supplies for all devices.
Single-Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
SSTL25 (Class I)
SSTL18 (Class I)
HSTL18(Class I)
Differential Interfaces
LVDS
BLVDS, MLVDS, RSDS
LVPECL
Differential SSTL18
Differential SSTL25
Differential HSTL18
1. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers.
2. These interfaces can be emulated with external resistors in all devices.
1, 2
2
Output Standard
2
2-25
V
CCIO
2.5, 3.3
3.3
3.3
2.5
1.8
1.5
1.2
3.3
2.5
1.8
1.8
2.5
3.3
1.8
2.5
1.8
—
—
—
—
—
(Typ.)
MachXO2 Family Data Sheet
Architecture