PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 94

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-34. 32-bit Target Single Write Transaction with a 64-bit Local Interface
Configuration Read and Write Transactions
The PCI IP core handles configuration transactions from addresses 00h to 40h. The Local Target Interface has no
control of these types of accesses and is independent these transactions. However, these transactions are still pro-
vided for verification purposes.
The PCI IP core only supports 32-bit, single data phase transactions to configuration registers. An individual idsel
signal is connected to each PCI IP core device. Otherwise, read and write transactions are like the standard mem-
ory and I/O transactions.
Table 2-36
The Capabilities List accesses and other configuration accesses over address 40h are beyond the PCI IP core’s
ability to complete the transaction without intervention from the Local Target Interface. Therefore, accesses to
memory locations over address 40h are treated as local accesses and handled by the local target interface control.
These configuration accesses are discussed further in Advanced Configuration Accesses section.
CLK
1
2
3
4
5
6
7
8
shows an example of a configuration write.
Turn around
PCI Data
Address
Phase
Data 1
Data 2
Wait
Wait
Wait
Idle
Figure 2-30
The master asserts framen and drives ad[31:0] and cben[3:0].
The master drives the first byte enables (Byte Enable 1). If the master is ready to write data, it
asserts irdyn and drives the first DWORD (Data 1) on ad[31:0].
The Core starts to decode the address and command. The Core drives the lt_address_out and
lt_command_out to the back-end.
If there is an address match, the Core drives the bar_hit signals to the back-end. The back-end
can use the bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on clock after bar_hit. If the
back-end will be ready to write data in two cycles, it can assert lt_rdyn.
trdyn is asserted since lt_rdyn was asserted the previous cycle.
Quad Word Aligned
The Core keeps trdyn asserted and puts Data 1 on the lower DWORD of lt_data_out.
If both irdyn and trdyn are asserted on the previous cycle, the master drives the next byte
enables (Byte Enable 2) on cben[3:0]. If the PCI master is still ready to write data, it keeps
irdyn asserted and drives the next DWORD (Data 2) on ad[31:0].
If both irdyn and trdyn were asserted on the previous cycle, the Core asserts
lt_ldata_xfern to the back-end to signify that Data 1 is valid. With lt_ldata_xfern
asserted, the back-end doesn’t write the data or increment the address counter.
Double Word Aligned
The Core keeps trdyn asserted and puts Data 1 on the upper DWORD of lt_data_out.
If both irdyn and trdyn are asserted on the previous cycle, the master drives the next byte
enables (Byte Enable 2) on cben[3:0]. If the master is still ready to write data, it keeps irdyn
asserted and drives the next DWORD (Data 2) on ad[31:0].
If irdyn, trdyn and lt_rdyn are asserted on the previous cycle, the Core asserts
lt_hdata_xfern to the back-end to signify that Data 1 is valid. With lt_hdata_xfern
asserted, the back-end can safely write the QWORD (Don’t care and Data 1) and increment the
address counter.
If both irdyn and trdyn are asserted on the previous cycle, the master relinquishes control of
framen, ad[31:0] and cben[3:0].
It also de-asserts irdyn if both trdyn and irdyn were asserted last cycle.It de-asserts both
devseln and trdyn if both trdyn and irdyn were asserted last cycle.
The Core relinquishes control of devseln and trdyn.The target signals to the back-end that the
transaction is complete by clearing bar_hit. It also de-asserts lt_data_xfern.
and
Table 2-35
illustrate an example of a configuration read.
94
Description
Functional Description
PCI IP Core User’s Guide
Figure 2-31
and