LCMXO2-4000ZE-3FTG256C Lattice, LCMXO2-4000ZE-3FTG256C Datasheet - Page 16
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LCMXO2-4000ZE-3FTG256C
Manufacturer Part Number
LCMXO2-4000ZE-3FTG256C
Description
FPGA - Field Programmable Gate Array 4320 LUTs 207 IO 1.2V 3 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000ZE-3FTG256C
Rohs
yes
Maximum Operating Frequency
133 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
BGA-256
Minimum Operating Temperature
0 C
Operating Supply Current
128 uA
Factory Pack Quantity
90
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000ZE-3FTG256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
The EBR memory supports three forms of write behavior for single or dual port operation:
1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current
2. Write Through – A copy of the input data appears at the output of the same port. This mode is supported for
3. Read-Before-Write – When new data is being written, the old contents of the address appears at the output.
FIFO Configuration
The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out,
RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The
Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.
Table 2-7 shows the range of programming values for these flags.
Table 2-7. Programmable FIFO Flag Ranges
The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset
that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset
state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is
in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from
the FIFO.
Memory Core Reset
The memory core contains data output latches for ports A and B. These are simple latches that can be reset syn-
chronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with
port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and
associated resets for both ports are as shown in Figure 2-9.
Figure 2-9. Memory Core Reset
address) does not appear on the output. This mode is supported for all data widths.
all data widths.
Full (FF)
Almost Full (AF)
Almost Empty (AE)
Empty (EF)
N = Address bit width.
GSRN
RSTA
RSTB
Programmable Disable
Flag Name
Memory Core
2-12
Programming Range
1 to max (up to 2
Output Data
D
D
Latches
SET
SET
Q
Q
1 to Full-1
1 to Full-1
0
MachXO2 Family Data Sheet
Port A[18:0]
Port B[18:0]
N
-1)
Architecture