LFE3-35EA-7LFTN256I Lattice, LFE3-35EA-7LFTN256I Datasheet - Page 7
LFE3-35EA-7LFTN256I
Manufacturer Part Number
LFE3-35EA-7LFTN256I
Description
FPGA - Field Programmable Gate Array 33.3K LUTs 133 I/O 1.2V -7 SPEED
Manufacturer
Lattice
Datasheet
1.LFE3-95EA-7LFN672I.pdf
(141 pages)
Specifications of LFE3-35EA-7LFTN256I
Rohs
yes
Factory Pack Quantity
90
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-35EA-7LFTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-3. Slice Diagram
Table 2-2. Slice Signal Descriptions
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
Function
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Routing
From
Inter-PFU signal
Inter-slice signal
Inter-slice signal
Inter-PFU signal
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Data signals
Data signals
Data signals
Data signals
Data signal
Data signal
Type
FXB
FXA
CLK
LSR
M1
M0
CE
C1
D1
C0
D0
A1
B1
A0
B0
* Not in Slice 3
For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2
WAD [A:D] is a 4-bit address from slice 2 LUT input
A0, B0, C0, D0
A1, B1, C1, D1
Signal Names
Q0, Q1
F0, F1
OFX0
OFX1
FCO
LSR
CLK
FXA
FXB
M0
M1
CE
FC
FCO To Different Slice/PFU
FCI From Different Slice/PFU
CARRY*
CARRY*
LUT4 &
LUT4 &
Inputs to LUT4
Inputs to LUT4
Multipurpose Input
Multipurpose Input
Clock Enable
Local Set/Reset
System Clock
Fast Carry-in
Intermediate signal to generate LUT6 and LUT7
Intermediate signal to generate LUT6 and LUT7
LUT4 output register bypass signals
Register outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT8
Slice 2 of each PFU is the fast carry chain output
CO
CO
CI
CI
2-4
F/SUM
F/SUM
1
LUT5
Mux
LatticeECP3 Family Data Sheet
Description
2
MUX depending on the slice
D
D
FF*
FF*
SLICE
Routing
OFX1
F1
Q1
To
OFX0
F0
Q0
1
Architecture
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