LFE2-6E-6T144I Lattice, LFE2-6E-6T144I Datasheet - Page 81
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LFE2-6E-6T144I
Manufacturer Part Number
LFE2-6E-6T144I
Description
FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -6 I
Manufacturer
Lattice
Datasheet
1.LFE2-70E-7F900C.pdf
(104 pages)
Specifications of LFE2-6E-6T144I
Number Of I/os
90
Maximum Operating Frequency
357 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Package / Case
TQFP-144
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
300
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-6E-6T144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
For Left and Right Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
For Bottom Edge of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
P[Edge] [n+4]
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 15 bits
PICs Associated with
of data for the left and right edges and up to 17 bits of data for the bottom edge. In some
packages, all the potential DDR data (DQ) pins may not be available. PIC numbering
definitions are provided in the “Signal Names” column of the Signal Descriptions table.
DQS Strobe
PIO Within PIC
4-3
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DDR Strobe (DQS) and
LatticeECP2 Family Data Sheet
Data (DQ) Pins
[Edge]DQSn
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Pinout Information
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