LFXP3C-3T144C Lattice, LFXP3C-3T144C Datasheet - Page 15
LFXP3C-3T144C
Manufacturer Part Number
LFXP3C-3T144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V -3 Spd
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T144C.pdf
(130 pages)
Specifications of LFXP3C-3T144C
Number Of I/os
100
Maximum Operating Frequency
320 MHz
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-144
Minimum Operating Temperature
0 C
Factory Pack Quantity
300
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3T144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Table 2-6. sysMEM Block Configurations
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-14 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
Single Port
True Dual Port
Pseudo Dual Port
Memory Mode
2-12
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
256 x 36
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
512 x 18
LatticeXP Family Data Sheet
Architecture
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