MAX13108EETL+ Maxim Integrated Products, MAX13108EETL+ Datasheet - Page 13

• Manufacturer Part Number: MAX13108EETL+
• Description: IC TRANSL LOGIC 16CH 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX13108EETL+

• Logic Function: Translator, Bidirectional, 3-State
• Number Of Bits: 16
• Input Type: CMOS
• Output Type: CMOS
• Data Rate: 20Mbps
• Number Of Channels: 16
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 20ns
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TQFN Exposed Pad
• Supply Voltage: 1.65 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX13101E/MAX13102E/MAX13103E/MAX13108E
logic-level translators provide the level shifting neces-
sary to allow data transfer in a multivoltage system.
Externally applied voltages, V
levels on either side of the device. Logic signals pre-
sent on the V
voltage logic signal on the V
vice-versa. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E are bidirectional level translators allowing
data translation in either direction (V
any single data line. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E accept V
All devices have a V
making them ideal for data transfer between low-volt-
age ASICs/PLDs and higher voltage systems.
The MAX13101E/MAX13102E/MAX13103E feature an
output enable mode that reduces V
less than 1µA, and V
when in shutdown. The MAX13108E features a multi-
plexing input that selects one byte between the two,
thus allowing multiplexing of the signals. The
MAX13101E/MAX13102E/MAX13103E/MAX13108E
have ±15kV ESD protection on the I/O V
greater protection in applications that route signals
externally. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E operate at a guaranteed data rate of
20Mbps. The maximum data rate depends heavily
on the load capacitance (see the Typical Operating
Characteristics ) and the output impedance of the
external driver.
For proper operation, ensure that +1.65V ≤ V
+1.2V ≤ V
sequencing, V
When V
10mA of current can be sourced to each load on the V
side, yet the device does not latch up. To guarantee that
no excess leakage current flows and that the device
does not interfere with the I/O on the V
be connected to GND with a max 50Ω resistor when the
V
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
architecture is based on a one-shot accelerator output
stage (Figure 6). Accelerator output stages are always
in tri-state except when there is a transition on any of
the translators on the input side, either I/O V
I/O V
which the accelerator output stages become active and
charge/discharge the capacitances at the I/Os. Due to
CC
supply is not present (Figure 5).
CC
CC
_. Then a short pulse is generated, during
L
is disconnected and V
≤ +5.5V, and V
L
Power-Supply Sequencing
L
side of the device appear as a higher
≥ V
______________________________________________________________________________________
CC
L
Input Driver Requirements
CC
Detailed Description
supply current to less than 2µA
does not damage the device.
range from +1.65V to +5.5V,
L
CC
≤ V
CC
side of the device, and
L
CC
and V
L
is powering up, up to
CC
from +1.2V to V
. During power-up
L
supply current to
side, V
L
, set the logic
L
CC
CC
↔ V
CC
≤ +5.5V,
side for
CC
should
L
16-Channel Buffered CMOS
) on
_ or
CC
L
.
Logic-Level Translators
the bidirectional nature, both input stages become
active during the one-shot pulse. This can lead to some
current feeding into the external source that is driving
the translator. However, this behavior helps to speed
up the transition on the driven side.
For proper full-speed operation, the output current of a
device that drives the inputs of the MAX13101E/
MAX13102E/MAX13103E/MAX13108E should meet the
following requirement:
where, i is the driver output current, V is the logic-supply
voltage (i.e., V
tance of the signal line.
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when driven low, places the
device into shutdown mode. During shutdown, the
MAX13101E I/O V
with internal 6kΩ resistors and the I/O V
tri-state. MAX13102E I/O V
the I/OV
6kΩ resistors. All I/O V
MAX13103E enter tri-state while the device is in shut-
down mode. During shutdown, the V
reduces to less than 1µA, and the V
reduces to less than 2µA. To guarantee minimum shut-
down supply current, all I/O V
GND or V
resistors. All I/O V
V
Drive EN to logic-high (V
Figure 5. Recommended Circuit for Powering Down V
CC,
DISABLE
V
BATT
or pulled to GND or V
L
R
DSON
_ lines are pulled down to ground with internal
L
, or pulled to GND or V
< 50Ω
L
i > 10
or V
V
CC
CC
SUPPLY
CC
CC
_ ports are pulled down to ground
8
_ need to be driven to GND or
Enable Output Mode (EN)
x V x (C + 10pF)
) and C is the parasitic capaci-
CC
L
or V
I/O V
I/O V
CC
_ and I/O V
CC
V
CC
CC
CC
_ lines enter tri-state and
CC
L
through 100kΩ resistors.
1
16
MAX13101E
MAX13102E
MAX13103E
MAX13108E
_ need to be driven to
) for normal operation.
GND
CC
L
+1.2V TO +5.5V
L
I/O V
through 100kΩ
L
I/O V
supply current
_ lines on the
supply current
L
V
L
_ ports enter
L
16
L
1
CC
13