5AGZME5K3F40C4N Altera Corporation, 5AGZME5K3F40C4N Datasheet - Page 26

• Manufacturer Part Number: 5AGZME5K3F40C4N
• Description: FPGA - Field Programmable Gate Array FPGA - Arria V GZ 15096 LABS 674 IOs
• Manufacturer: Altera Corporation
• Series: Arria V GZr

Specifications of 5AGZME5K3F40C4N

• Rohs: yes
• Number Of Logic Blocks: 15096
• Number Of I/os: 674
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.2 V to 1.8 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1517
• Distributed Ram: 33518 kbit
• Minimum Operating Temperature: 0 C

Altera Corporation
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Table 22: Transceiver PCS Features for Arria V GZ Devices
Custom PHY
GPON
Custom 10G PHY
PCIe Gen1
(x1, x4, x8)
PCIe Gen2
(x1, x4, x8)
PCIe Gen3
(x1, x4, x8)
10GbE
Interlaken
Arria V Device Overview
Protocol
3.125 to 12.5
1.25 and 2.5
9.98 to 12.5
2.5 and 5.0
Data Rates
0.6 to 9.80
10.3125
(Gbps)
8.0
Transmitter Data Path Features
Phase compensation FIFO
Byte serializer
8B/10B encoder
Bit-slip
Channel bonding
TX FIFO
Gear box
Bit-slip
Phase compensation FIFO
Byte serializer
8B/10B encoder
Bit-slip
Channel bonding
PIPE 2.0 interface to core
logic
Phase compensation FIFO
128B/130B encoder
Scrambler
Gear box
Bit-slip
TX FIFO
64B/66B encoder
Scrambler
Gear box
TX FIFO
Frame generator
CRC-32 generator
Scrambler
Disparity generator
Gear box
Receiver Data Path Features
Word aligner
Deskew FIFO
Rate match FIFO
8B/10B decoder
Byte deserializer
Byte ordering
RX FIFO
Gear box
Word aligner
Deskew FIFO
Rate match FIFO
8B/10B decoder
Byte deserializer,
Byte ordering
PIPE 2.0 interface to core
logic
Block synchronization
Rate match FIFO
128B/130B decoder
Descrambler
Phase compensation FIFO
RX FIFO
64B/66B decoder
Descrambler
Block synchronization
Gear box
RX FIFO
Frame generator
CRC-32 checker
Frame decoder
Descrambler
Disparity checker
Block synchronization
Gear box
Arria V Device Overview
2013.01.11
AV-51001