iCE65L01F-LVQ100I Lattice, iCE65L01F-LVQ100I Datasheet - Page 67
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
iCE65L01F-LVQ100I
Manufacturer Part Number
iCE65L01F-LVQ100I
Description
FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
Manufacturer
Lattice
Datasheet
1.ICE65L04F-TCB196C.pdf
(110 pages)
Specifications of iCE65L01F-LVQ100I
Rohs
yes
Number Of Gates
1280
Number Of Logic Blocks
16
Number Of I/os
72
Maximum Operating Frequency
256 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-100
Distributed Ram
64 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
12 uA
Factory Pack Quantity
90
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICE65L01F-LVQ100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor Corporation
www.latticesemi.com
CB196 Chip-Scale Ball-Grid Array
The CB196 package is a chip-scale, fully-populated, ball-grid array with 0.5 mm ball pitch.
Footprint Diagram
Figure 45
iCE65L08 is different than the iCE64L04 footprint, as shown in
warning diamonds () in the footprint diagrams and summarized in
Figure 31
ball chip-scale BGA packages. The signal pins are also grouped into the four I/O Banks and the SPI interface.
!
A
B
C
D
E
F
G
H
J
K
L
M
N
P
shows the conventions used in the diagram. Also see
shows the iCE65L04 chip-scale BGA footprint for the 8 x 8 mm CB196 package. The footprint for the
DP00B
DP00A
DP02A
DP03A
DP10A
VCCIO_3
DP14A
DP15A
DP17A
PIO0 PIO0 PIO0 PIO0
GND
GBIN7/
DP07B
GBIN6/
DP08A
PIO2 PIO2 PIO2 PIO2
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
1
1
Although both the iCE65L04 and iCE65L08 are both available in the CB196 package and
completely pin compatible, there are differences as shown in
DP02B
DP03B
DP07A
DP08B
DP10B
DP12A
DP14B
DP15B
DP17B
PIO0
GND
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
VCC
Figure 45:
2
2
VCCIO_3
DP01B
DP01A
DP05A
DP09A
DP11B
DP12B
DP16A
PIO0 PIO0
GND
PIO2 PIO2
PIO2 PIO2 PIO2 PIO2
PIO1/
PIO1/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
3
3
DP04A
DP04B
DP05B
DP09B
DP11A
DP16B
PIO0
PIO2 PIO2 PIO2
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
VCC
iCE65L04 CB196 Chip-Scale BGA Footprint (Top View)
4
4
I/O Bank 2
VCCIO_2
GBIN5/
DP06B
DP06A
DP13B
DP13A
PIO0
PIO0
PIO0
PIO0
PIO3/
PIO3/
PIO3/
PIO3/
GND
PIO2 PIO2 PIO2 PIO2 PIO2
PIO2
5
5
I/O Bank 0
VCCIO_0
VCCIO_3
PIO0
PIO0
PIO0
PIO0
PIO0
PIO2 PIO2
GND GND GND
GND
VCC
6
6
GBIN0/
GBIN1/
GBIN4/
PIO0
PIO0
PIO0
PIO0
GND VCC
GND GND GND
PIO2
PIO2
VCC
VCC
VCC
7
7
VCCIO_0
PIO0
PIO0
PIO0
PIO0
PIO2
PIO2
PIO2
PIO2
GND
8
8
VCCIO_1
VCCIO_2
CBSEL0
PIO2/
GND
PIO0
PIO0
PIO0
PIO0
PIO2
PIO2
PIO2
VCC
Figure
Table 42
9
9
CRESET_B
GBIN2/
VCCIO_2
CBSEL1
CDONE
PIO2/
Table
PIO0 PIO0
PIO0
PIO0
PIO0
PIO1
PIO1
PIO1
PIO1
PIO1
GND
10 11 12 13 14
10 11 12 13 14
46. The pinout differences are highlighted by
for a complete, detailed pinout for the 196-
Table
43.
PIOS/
SPI_SO
PIOS/
PIO0
PIO0
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO2 PIO2 PIO2
SPI_SI
SPI_
VCC
SPI Bank
43.
SPI_SCK
GBIN3/
PIOS/
PIO0
GND
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
TCK
TDI
SPI_SS_B
PIOS/
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1 PIO1
PIO1
PIO1
PIO1
PIO1
VPP_
FAST
VCC
(2.42, 30-MAR-2011)
VCCIO_1
TRST_B
PIO1
PIO1
PIO1
PIO1
PIO1
GND
PIO1
PIO1
VPP_
TDO
TMS
2V5
A
B
C
D
E
F
G
H
J
K
L
M
N
P
almost
67