iCE65L01F-TCB132I Lattice, iCE65L01F-TCB132I Datasheet - Page 50
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iCE65L01F-TCB132I
Manufacturer Part Number
iCE65L01F-TCB132I
Description
FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
Manufacturer
Lattice
Datasheet
1.ICE65L04F-TCB196C.pdf
(110 pages)
Specifications of iCE65L01F-TCB132I
Rohs
yes
Number Of Gates
1280
Number Of Logic Blocks
16
Number Of I/os
93
Maximum Operating Frequency
256 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
CBGA-132
Distributed Ram
64 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
12 uA
Factory Pack Quantity
384
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICE65L01F-TCB132I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
50
VQ100 Very-thin Quad Flat Package
The VQ100 package is a very-thin quad-flat package with 0.5 mm lead pitch. The iCE65L01 and iCE65L04 devices
are available in this package.
Footprint Diagram
Figure 36
complete, detailed pinout for the 100-lead very-thin quad-flat package. The signal pins are also grouped into the
four I/O Banks and the SPI interface.
Pinout Table
Table 39
pin function. The table also highlights the differential I/O pairs in I/O Bank 3. The VQ100 package has no JTAG
pins.
GBIN7/
GBIN6/
provides a detailed pinout table for the VQ100 package. Pins are generally arranged by I/O bank, then by
shows the footprint diagram for the 100-lead very-thin quad-flat package (VQ100). See Table 40 for a
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3/
PIO3
PIO3
VCCIO_3
VCCIO_3
VCCIO_3
/DP04B
/DP05A
DP00A
DP00B
DP01A
DP01B
DP02A
DP02B
DP03A
DP03B
DP04A
DP05B
DP06A
DP06B
DP07A
DP07B
DP08A
DP08B
GND
GND
GND
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Figure 36: iCE65 VQ100 Footprint (Top View)
Pin 1 indicator
iCE65L04F-L
VQ100
SiliconBlue
I/O Bank 2
(L01 only, see Table 40)
(L01 only, see Table 39)
I/O Bank 0
™
Family
Lattice Semiconductor Corporation
R
SPI Bank
www.latticesemi.com
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VPP_2V5
PIO1
PIO1
PIO1
PIO1
GND
PIO1
PIO1
VCCIO_1
PIO1
PIO1
PIO1
GBIN2/
GBIN3/
VCC
PIO1
PIO1
VCCIO_1
PIO1
PIO1
GND
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1