MC100EP91DWG ON Semiconductor, MC100EP91DWG Datasheet

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MC100EP91DWG

Manufacturer Part Number
MC100EP91DWG
Description
TRANSLATOR NECL OUTPUT 20-SOIC
Manufacturer
ON Semiconductor
Series
100EPr
Datasheet

Specifications of MC100EP91DWG

Logic Function
Translator
Number Of Bits
3
Input Type
AnyLevel™
Output Type
NECL
Number Of Channels
3
Number Of Outputs/channel
1
Differential - Input:output
Yes/Yes
Propagation Delay (max)
0.675ns
Voltage - Supply
2.375 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Supply Voltage
2.375 V ~ 3.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
MC100EP91
2.5 V/3.3 V Any Level
Positive Input to
-3.3 V/-5.5 V NECL Output
Translator
Description
translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL,
CML or LVDS signals, and translates them to differential NECL
output signals (−3.0 V / −5.5 V).
rails. The V
and the V
The GND pins are connected to the system ground plane. Both V
and V
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
this device only. For single-ended input conditions, the unused
differential input is connected to V
V
and V
to 0.5 mA. When not used, V
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. 3
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
BB
The MC100EP91 is a triple any level positive input to NECL output
To accomplish the level translation the EP91 requires three power
Under open input conditions, the D input will be biased at V
The V
V
Maximum Input Clock Frequency > 2.0 GHz Typical
Maximum Input Data Rate > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range: V
Q Output will Default LOW with Inputs Open or at GND
Pb−Free Packages are Available*
EE
may also rebias AC coupled inputs. When used, decouple V
CC
CC
= −3.0 V to −5.5 V; GND = 0 V
BB
should be bypassed to ground via 0.01 mF capacitors.
via a 0.01 mF capacitor and limit current sourcing or sinking
EE
CC
pin, an internally generated voltage supply, is available to
pin should be connected to the negative power supply.
pins should be connected to the positive power supply,
CC
= 2.375 V to 3.8 V;
BB
should be left open.
BB
as a switching reference voltage.
1
CC
BB
EE
/2
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
20
*For additional marking information, refer to
DW SUFFIX
CASE 751D
SO−20 WB
(Note: Microdot may be in either location)
Application Note AND8002/D.
24 PIN QFN
MN SUFFIX
CASE 485L
24
ORDERING INFORMATION
1
A
WL, L
YY, Y
WW, W = Work Week
G or G
1
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
20
MARKING DIAGRAMS*
1
Publication Order Number:
1
AWLYYWWG
MC100EP91
24
ALYWG
MC100EP91/D
EP91
100
G

Related parts for MC100EP91DWG

MC100EP91DWG Summary of contents

Page 1

... Q Output will Default LOW with Inputs Open or at GND • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 July, 2008 − Rev. 3 ...

Page 2

Positive Level Table 1. PIN DESCRIPTION Pin SOIC QFN Name 15 14, 17 19, 20, 23, GND ...

Page 3

GND MC100EP91 Figure 2. SOIC−20 Lead Pinout (Top View) *All and GND pins must ...

Page 4

Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply CC V Negative Power Supply EE V Positive Input Voltage I V Operating Voltage OP I Output Current out I PECL V Sink/Source Operating Temperature Range A ...

Page 5

Table 5. DC CHARACTERISTICS POSITIVE INPUT Symbol Characteristic I Positive Power Supply Current CC V Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended PECL Output Voltage Reference BB V Input HIGH Voltage Common Mode Range IHCMR ...

Page 6

Table 7. AC CHARACTERISTICS V Symbol Characteristic V Output Voltage Amplitude OUTPP (Figure 4) (Note 9) t Propagation Delay PLH PHL0 t Pulse Skew (Note 10) SKEW Output−to−Output (Note 11) Part−to−Part (Diff) (Note 11) t RMS ...

Page 7

Application Information All MC100EP91 inputs can accept LVPECL, LVTTL, LVCMOS, HSTL, CML, or LVDS signal levels. The limitations for differential input signal (LVDS, HSTL, LVPECL, or CML) are the minimum input swing of 150 LVPECL Driver ...

Page 8

... ORDERING INFORMATION Device MC100EP91DW MC100EP91DWG MC100EP91DWR2 MC100EP91DWR2G MC100EP91MN MC100EP91MNG MC100EP91MNR2 MC100EP91MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Q Driver Device Q Figure 12. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − ...

Page 9

20X 0. 18X A1 T PACKAGE DIMENSIONS SO−20 WB CASE 751D−05 ISSUE G q NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS ...

Page 10

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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