iCE65L08F-LCB132C Lattice, iCE65L08F-LCB132C Datasheet - Page 16
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iCE65L08F-LCB132C
Manufacturer Part Number
iCE65L08F-LCB132C
Description
FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
Manufacturer
Lattice
Datasheet
1.ICE65L04F-TCB196C.pdf
(110 pages)
Specifications of iCE65L08F-LCB132C
Rohs
yes
Number Of Gates
7680
Number Of Logic Blocks
32
Number Of I/os
95
Maximum Operating Frequency
256 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
CBGA-132
Distributed Ram
128 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
54 uA
Factory Pack Quantity
384
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICE65L08F-LCB132C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
16
Input and Output Register Control per PIO Pair
Figure 11:
PIO pins are grouped into pairs for synchronous control. Registers within pairs of PIO pins share common input
clock, output clock, and I/O clock enable control signals, as illustrated in
are removed from the drawing for clarity.
The INCLK clock signal only controls the input flip-flops within the PIO pair.
The OUTCLK clock signal controls the output flip-flops and the output-enable flip-flops within the PIO pair.
If desired in the iCE65 application, the INCLK and OUTCLK signals can be connected together.
The IOENA clock-enable input, if used, enables all registers in the PIO pair, as shown in
registers are always enabled.
The pairing of PIO pairs is most evident in the tables in
!
PIO Pairs Share Clock and Clock Enable Controls (only registered paths shown for clarity)
Before laying out your printed-circuit board, run the design through the iCEcube development software to
verify that your selected pinout complies with these I/O register pairing requirements. See
Cross
Reference” starting on page 84.
OUTCLK
IOENA
INCLK
OUT
OUT
OE
OE
IN
IN
= Statically defined by configuration program
EN
EN
1
™
Family
“Die Cross
EN
EN
EN
EN
Reference” starting on page 84.
Figure
Lattice Semiconductor Corporation
0 = Hi-Z
1 = Output Enabled
0 = Hi-Z
1 = Output Enabled
11. The combinational logic paths
PIO Pair
PAD
PAD
Figure
www.latticesemi.com
tables in
11. By default, the
“Die