KSZ8041TLI-S Micrel, KSZ8041TLI-S Datasheet - Page 23

• Manufacturer Part Number: KSZ8041TLI-S
• Description: Ethernet ICs Physical Layer Transceiver 10/100BASE-FX (Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8041TLI-S

• Rohs: yes
• Product: Ethernet Transceivers
• Package / Case: TQFP-48
• Mounting Style: SMD/SMT

Micrel, Inc.
RMII Signal Definition
The following table describes the RMII signals. Refer to RMII Specification for detailed information.
Reference Clock (REF_CLK)
REF_CLK is sourced by the MAC or system board. It is a continuous 50 MHz clock that provides the timing reference for
TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER.
Transmit Enable (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final di-bit of a frame.
TX_EN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is ”00” to indicate idle when TX_EN is de-asserted. Values other than “00” on TXD[1:0]
while TX_EN is de-asserted are ignored by the PHY.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of the
frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers
two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other
than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC.
Receive Error (RX_ER)
RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the
MAC.
April 2007
RMII
Signal Name
REF_CLK
TX_EN
TXD[1:0]
CRS_DV
RXD[1:0]
RX_ER
Direction
(with respect to PHY,
KSZ8041TL/FTL signal)
Input
Input
Input
Output
Output
Output
Table 3. RMII Signal Description
Direction
(with respect to MAC)
Input, or Output
Output
Output
Input
Input
Input, or (not required)
23
Description
Synchronous 50 MHz clock reference for
receive, transmit and control interface
Transmit Enable
Transmit Data [1:0]
Carrier Sense/Receive Data Valid
Receive Data [1:0]
Receive Error
M9999-042707-1.1
KSZ8041TL/FTL