1893AFLFT IDT, 1893AFLFT Datasheet
1893AFLFT
Specifications of 1893AFLFT
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1893AFLFT Summary of contents
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Integrated Circuit Systems, Inc. 3.3-V 10Base-T/100Base-TX Integrated PHYceiver General The ICS1893AF is a lower cost, re-packaged version of the ICS1893Y-10. The ICS1893AF is a fully integrated, Physical Layer device (PHY) that is compliant with both the 10Base-T and 100Base-TX CSMA/CD ...
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ICS1893AF Data Sheet - Release Section Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms ......................................................................................... 10 Chapter 2 Conventions and Nomenclature..................................................................................... 12 Chapter 3 Typical ICS1893AF Applications..................................................................................... 14 3.1 ICS1893AF / ICS1893Y-10 Pin Differences ...........................................................14 3.2 ICS1893AF / ICS1893Y-10 ...
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ICS1893AF Data Sheet - Release Section 7.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................................40 7.3.1 PCS Sublayer ........................................................................................................40 7.3.2 PMA Sublayer ........................................................................................................40 7.3.3 PCS/PMA Transmit Modules .................................................................................41 7.3.4 PCS/PMA Receive Modules ..................................................................................42 7.3.5 PCS Control Signal Generation .............................................................................43 7.3.6 ...
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ICS1893AF Data Sheet - Release Section Chapter 8 Management Register Set ............................................................................................... 55 8.1 Introduction to Management Register Set .............................................................56 8.1.1 Management Register Set Outline .........................................................................56 8.1.2 Management Register Bit Access ..........................................................................57 8.1.3 Management Register Bit Default Values ..............................................................57 8.1.4 ...
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ICS1893AF Data Sheet - Release Section 8.5 Register 3: PHY Identifier Register ........................................................................70 8.5.1 OUI bits 19-24 (bits 3.15:10) ..................................................................................70 8.5.2 Manufacturer’s Model Number (bits 3.9:4) .............................................................71 8.5.3 Revision Number (bits 3.3:0) .................................................................................71 8.6 Register 4: Auto-Negotiation Register ...................................................................72 8.6.1 ...
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ICS1893AF Data Sheet - Release Section 8.11 Register 16: Extended Control Register ................................................................84 8.11.1 Command Override Write Enable (bit 16.15) .........................................................85 8.11.2 ICS Reserved (bits 16.14:11) .................................................................................85 8.11.3 PHY Address (bits 16.10:6) ...................................................................................85 8.11.4 Stream Cipher Scrambler Test Mode (bit ...
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ICS1893AF Data Sheet - Release Section 8.14 Register 19: Extended Control Register 2 .............................................................96 8.14.1 Node/Repeater Configuration (bit 19.15) ...............................................................97 8.14.2 Hardware/Software Priority Status (bit 19.14) ........................................................97 8.14.3 Remote Fault (bit 19.13) ........................................................................................97 8.14.4 ICS Reserved (bits 19.12:8) ...................................................................................97 8.14.5 ...
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ICS1893AF Data Sheet - Release Section 10.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion ......127 10.5.15 Reset: Power-On Reset .......................................................................................128 10.5.16 Reset: Hardware Reset and Power-Down ...........................................................129 10.5.17 10Base-T: Heartbeat Timing (SQE) .....................................................................130 10.5.18 10Base-T: Jabber Timing .....................................................................................131 10.5.19 10Base-T: Normal ...
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ICS1893AF Data Sheet - Release Revision History • The initial release of this document was dated 5 April 2002. • This release of this document, Rev B, is dated 6 March 2003. The following list indicates where changes occur. – ...
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ICS1893AF Data Sheet - Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National ...
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ICS1893AF Data Sheet - Release Table 1-1. Abbreviations and Acronyms (Continued) Abbreviation / Acronym OSI Open Systems Interconnection OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893AF is a physical-layer device, also referred ...
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ICS1893AF Data Sheet - Release Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Bits Code groups Colon (:) Numbers Pin (or signal) names ...
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ICS1893AF Data Sheet - Release Table 2-1. Conventions and Nomenclature (Continued) Item Signal references Symbols Terms: ‘set’, ‘active’, ‘asserted’, Terms: ‘cleared’, ‘de-asserted’, ‘inactive’ Terms: ‘twisted-pair receiver’ Terms: ‘twisted-pair transmitter’ ICS1893AF, Rev. D 10/26/04 Convention / Nomenclature • When referring to ...
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ICS1893AF Data Sheet - Release Chapter 3 Typical ICS1893AF Applications The ICS1893AF is configured for the majority of single Phy Ethernet applications. These applications include Network Interface Cards, PC Motherboards, Printers, ACR Riser cards, Set top Boxes, and Game machines. ...
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ICS1893AF Data Sheet - Release – Hardwired for Node configuration (NOD/REP pin removed, tied internally to VSS). Node configuration enables the 10M SQE test default setting and causes CRS to be asserted for either transmit or receive activity in half ...
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ICS1893AF Data Sheet - Release Chapter 4 Overview of the ICS1893AF The ICS1893AF is a stream processor. During data transmission, it accepts sequential nibbles from its MAC (Media Access Control) converts them into a serial bit stream, encodes them, and ...
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ICS1893AF Data Sheet - Release 4.1 100Base-TX Operation During 100Base-TX data transmission, the ICS1893AF accepts packets from a MAC and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893AF encapsulates each MAC/repeater frame, including the ...
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ICS1893AF Data Sheet - Release Chapter 5 Operating Modes Overview The ICS1893AF operating modes are typically controlled from software. The ICS1893AF register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. The ICS1893AF is configured to ...
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ICS1893AF Data Sheet - Release 5.1 Reset Operations This section first discusses reset operations in general and then specific ways in which the ICS1893AF can be configured for various reset options. 5.1.1 General Reset Operations The following reset operations apply ...
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ICS1893AF Data Sheet - Release 5.1.2 Specific Reset Operations This section discusses the following specific ways that the ICS1893AF can be reset: • Hardware reset (using the RESETn pin) • Power-on reset (applying power to the ICS1893AF) • Software reset ...
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ICS1893AF Data Sheet - Release 5.1.2.3 Software Reset Entering Software Reset Initiation of a software reset occurs when a management entity writes a logic one to Control Register bit 0.15. When this write occurs, the ICS1893AF enters the reset state ...
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ICS1893AF Data Sheet - Release 5.3 Automatic Power-Saving Operations The ICS1893AF has power-saving features that automatically minimize its total power consumption while it is operating. Table 5-1 lists the ICS1893AF automatic power-saving features for the various modes. Table 5-1. Automatic ...
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ICS1893AF Data Sheet - Release 5.5 100Base-TX Operations The ICS1893AF 100Base-TX mode provides 100Base-TX physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1893AF is a 100M translator between a MAC and the ...
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ICS1893AF Data Sheet - Release Chapter 6 Interface Overviews The ICS1893AF MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: • Section 6.1, “MII Data Interface” • ...
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ICS1893AF Data Sheet - Release 6.1 MII Data Interface The ICS1893AF’s MAC Interface is the Medium Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. The ICS1893AF MAC/Repeater Interface is configured for the MII Data Interface mode, data ...
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ICS1893AF Data Sheet - Release 6.2 Serial Management Interface The ICS1893AF provides an ISO/IEC compliant, two-wire Serial Management Interface as part of its MAC/Repeater Interface. This Serial Management Interface is used to exchange control, status, and configuration information between a ...
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ICS1893AF Data Sheet - Release 6.3.1 Twisted-Pair Transmitter Interface The twisted-pair transmitter driver uses an H-bridge configuration. ICS suggests any of the following 1:1 10/100 Magnetics: • Halo TG22S012ND • Midcom 6120-37 Figure 6-1 shows the design for the ICS1893AF ...
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ICS1893AF Data Sheet - Release 6.3.2 Twisted-Pair Receiver Interface Figure 6-2 shows the design for the ICS1893AF twisted-pair receiver interface. • Two 56.2 1% resistors are in series, with the center bypassed to ground with a 0.1- F bypass capacitor. ...
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ICS1893AF Data Sheet - Release 6.4 Clock Reference Interface The REF_IN pin provides the ICS1893AF Clock Reference Interface. The ICS1893AF requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is necessary to ...
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ICS1893AF Data Sheet - Release If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893AF. A pair of bypass capacitors on either side of the ...
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ICS1893AF Data Sheet - Release 6.5 Status Interface The ICS1893AF provides five multi-function configuration pins that report the results of continual link monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see Table 6-3. Pins ...
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ICS1893AF Data Sheet - Release Figure 6-4 shows typical biasing and LED connections for the ICS1893AF. Figure 6-4. ICS1893AF LED - PHY Interface P4RD P3TD 8 6 REC TRANS 10K 10K This circuit decodes to PHY address = 1. Notes: ...
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ICS1893AF Data Sheet - Release Chapter 7 Functional Blocks This chapter discusses the following ICS1893AF functional blocks. • Section 7.1, “Functional Block: Media Independent Interface” • Section 7.2, “Functional Block: Auto-Negotiation” • Section 7.3, “Functional Block: 100Base-X PCS and PMA ...
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ICS1893AF Data Sheet - Release 7.1 Functional Block: Media Independent Interface All ICS1893AF MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the ICS1893AF MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) ...
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ICS1893AF Data Sheet - Release 7.2 Functional Block: Auto-Negotiation The auto-negotiation logic of the ICS1893AF has the following main functions: • To determine the capabilities of the remote link partner, (that is, the device at the other end of the ...
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ICS1893AF Data Sheet - Release 7.2.1 Auto-Negotiation General Process The Auto-Negotiation sublayer uses a physical signaling technique that is transparent at the packet level and all higher protocol levels. This technique builds on the link pulse mechanism employed in 10Base-T ...
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ICS1893AF Data Sheet - Release 7.2.2 Auto-Negotiation: Parallel Detection The ICS1893AF supports parallel detection therefore compatible with networks that do not support the auto-negotiation process. When enabled, the Auto-Negotiation sublayer can detect legacy 10Base-T link partners as well ...
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ICS1893AF Data Sheet - Release 7.2.4 Auto-Negotiation: Reset and Restart If enabled, execution of the ICS1893AF auto-negotiation process occurs at power-up and upon management request. There are two primary ways to begin the Auto-Negotiation state machine: • ICS1893AF reset • ...
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ICS1893AF Data Sheet - Release The ISO/IEC-defined priority table determines the established link type simpler alternative, the STA can read the QuickPoll Detailed Status Register and determine the link type from the Data Rate bit (bit 17.15) and ...
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ICS1893AF Data Sheet - Release 7.3 Functional Block: 100Base-X PCS and PMA Sublayers The ICS1893AF is fully compliant with clause 24 of the ISO/IEC specification, which defines the 100Base-X Physical Coding sublayer (PCS) and Physical Medium Attachment (PMA) sublayers. 7.3.1 ...
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ICS1893AF Data Sheet - Release 7.3.3 PCS/PMA Transmit Modules Both the PCS and PMA sublayers have Transmit modules. 7.3.3.1 PCS Transmit Module The ICS1893AF PCS Transmit module accepts nibbles from the MAC/Repeater Interface and converts the nibbles into 5-bit ‘code ...
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ICS1893AF Data Sheet - Release 7.3.4 PCS/PMA Receive Modules Both the PCS and PMA sublayers have Receive modules. 7.3.4.1 PCS Receive Module The ICS1893AF PCS Receive module accepts both a serial bit stream and a clock signal from the PMA ...
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ICS1893AF Data Sheet - Release 7.3.5 PCS Control Signal Generation For the PCS sublayer, there are two control signals: a Carrier Sense signal (CRS) and a Collision Detect signal (COL). The CRS control signals is generated as follows: 1. When ...
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ICS1893AF Data Sheet - Release 7.4 Functional Block: 100Base-TX TP-PMD Operations The ICS1893AF supports both 10Base-T and 100Base-TX operations. For 100Base-TX operations, the TP-PMD module performs stream-cipher scrambling/descrambling and MLT-3 encoding/decoding (3-level, multi-level transition) in compliance with the ANSI Standard ...
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ICS1893AF Data Sheet - Release 7.4.4 100Base-TX Operation: Adaptive Equalizer The ICS1893AF has a TP-PMD sublayer that uses adaptive equalization circuitry to compensate for signal amplitude and phase distortion incurred from the transmission medium data rate of 100 ...
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ICS1893AF Data Sheet - Release 7.4.7 100Base-TX Operation: Auto Polarity Correction The ICS1893AF can sense and then automatically correct a signal polarity that is reversed on its Twisted-Pair Receiver inputs. A signal polarity reversal occurs when the input signals on ...
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... The 10Base-T and 100Base-TX operations differ as follows. 10Base-T operations are fundamentally simpler than 100Base-TX operations. The data rate is slower, requiring less encoding than 100Base-TX operations. In addition, the bandwidth requirements (and therefore the line attenuation issues) are not as severe as with 100-MHz operations. Consequently, when an ICS1893AF is set for 10Base-T operations, it requires fewer internal circuits in contrast to 100Base-TX operations ...
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ICS1893AF Data Sheet - Release 7.5.4 10Base-T Operation: Idle An ICS1893AF transmits Normal Link Pulses (that is, 10Base-T Idles) on its MDI in the absence of data (that is, when the MAC/repeater is not requiring it to transmit any data). ...
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ICS1893AF Data Sheet - Release Note ICS1893AF receives ‘valid data’ when its Twisted-Pair Receiver phase-locked loop can acquire lock and extract the receive clock from the incoming data stream for a minimum of three consecutive bit times. 2. ...
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ICS1893AF Data Sheet - Release 7.5.9 10Base-T Operation: Jabber The ICS1893AF has an ISO/IEC compliant Jabber Detection Function that, when enabled, monitors the data stream sent to its Twisted-Pair Transmitter to ensure that it does not exceed the 10Base-T Jabber ...
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ICS1893AF Data Sheet - Release 7.5.11 10Base-T Operation: Twisted-Pair Transmitter The 10Base-T Twisted-Pair Transmitter is functionally similar to the 100Base-TX Twisted-Pair Transmitter. The primary differences are in the data rate and signaling, as specified in the ISO/IEC specifications. For more ...
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ICS1893AF Data Sheet - Release 7.6 Functional Block: Management Interface As part of the MAC/Repeater Interface, the ICS1893AF provides a two-wire serial management interface which complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used to ...
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ICS1893AF Data Sheet - Release 7.6.2.1 Management Frame Preamble The ICS1893AF continually monitors its serial management interface for either valid data or a Management Frame (MF) Preamble, based upon the setting of the MF Preamble Suppression bit, 1.6. When the ...
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... Write, an ICS1893AF waits while the STA transmits a logic one, followed by a logic zero on its MDIO pin. 7.6.2.8 Management Frame Data A valid management frame includes a 16-bit Data field for exchanging the register contents between the ICS1893AF and the STA. All Management Registers are 16 bits wide, matching the width of the Data field. During a transaction that is a: • ...
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ICS1893AF Data Sheet - Release Chapter 8 Management Register Set The tables in this chapter detail the functionality of the bits in the management register set. The tables include the register locations, the bit positions, the bit definitions, the STA ...
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ICS1893AF Data Sheet - Release 8.1 Introduction to Management Register Set This section explains in general terms the Management Register set discussed in this chapter. (For a summary of the Management Register set, see 8.1.1 Management Register Set Outline This ...
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ICS1893AF Data Sheet - Release 8.1.2 Management Register Bit Access The ICS1893AF Management Registers include one or more of the following types of bits: Table 8-3. Description of Management Register Bit Types Management Register Bit Types Symbol Read-Only Command Override ...
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ICS1893AF Data Sheet - Release 8.1.4 Management Register Bit Special Functions This section discusses the types of special functions for the Management Register bits. 8.1.4.1 Latching High Bits The purpose of a latching high (LH) bit is to record an ...
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ICS1893AF Data Sheet - Release 8.2 Register 0: Control Register Table 8-5 lists the bits for the Control Register, a 16-bit register used to establish the basic operating modes of the ICS1893AF. • The Control Register is accessible through the ...
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ICS1893AF Data Sheet - Release 8.2.2 Loopback Enable (bit 0.14) This bit controls the Loopback mode for the ICS1893AF. Setting this bit to logic: • Zero disables the Loopback mode. • One enables the Loopback mode by disabling the Twisted-Pair ...
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ICS1893AF Data Sheet - Release 8.2.5 Low Power Mode (bit 0.11) This bit provides one way to control the ICS1893AF low-power mode function. When bit 0.11 is logic: • Zero, there is no impact to ICS1893AF operations. • One, the ...
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ICS1893AF Data Sheet - Release 8.2.8 Duplex Mode (bit 0.8) This bit provides a means of controlling the ICS1893AF Duplex Mode. Its operation depends on several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). ...
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ICS1893AF Data Sheet - Release 8.3 Register 1: Status Register Table 8-6 lists the Status Register bits. These 16 bits of data provide an interface between the ICS1893AF and an STA. There are two types of status bits: some report ...
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ICS1893AF Data Sheet - Release 8.3.2 100Base-TX Full Duplex (bit 1.14) The STA reads this bit to learn if the ICS1893AF can support 100Base-TX, full-duplex operations. The ISO/IEC specification requires that the ICS1893AF must set bit 1.14 to logic: • ...
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ICS1893AF Data Sheet - Release 8.3.6 IEEE Reserved Bits (bits 1.10:7) The IEEE reserves these bits for future use. When an STA: • Reads a reserved bit, the ICS1893AF returns a logic zero. • Writes a reserved bit, the STA ...
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ICS1893AF Data Sheet - Release 8.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893AF sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ...
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ICS1893AF Data Sheet - Release 8.3.11 Link Status (bit 1.2) The purpose of this bit 1.2 (which is also accessible through the QuickPoll Detailed Status Register, bit 17. determine if an established link is dropped, even momentarily. To ...
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ICS1893AF Data Sheet - Release 8.4 Register 2: PHY Identifier Register Table 8-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC ...
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ICS1893AF Data Sheet - Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. The binary representation of an OUI is formed by ...
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ICS1893AF Data Sheet - Release 8.5 Register 3: PHY Identifier Register Table 8-9 lists the bits for PHY Identifier Register (Register 3), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC ...
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ICS1893AF Data Sheet - Release 8.5.2 Manufacturer’s Model Number (bits 3.9:4) The model number for the ICS1893AF is 4 (decimal stored in bit 3.9:4 as 00100b. 8.5.3 Revision Number (bits 3.3:0) Table 8-10 lists the valid ICS1893AF revision ...
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ICS1893AF Data Sheet - Release 8.6 Register 4: Auto-Negotiation Register Table 8-11 lists the bits for the Auto-Negotiation Register. An STA uses this register to select the ICS1893AF capabilities that it wants to advertise to its remote link partner. During ...
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ICS1893AF Data Sheet - Release When this reserved bit is read by an STA, the ICS1893AF returns a logic zero. However, whenever an STA writes to this reserved bit, it must use the default value specified in this data sheet. ...
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ICS1893AF Data Sheet - Release 8.6.5 Technology Ability Field (bits 4.9:5) When its Auto-Negotiation sublayer is enabled, the ICS1893AF transmits its link capabilities to its remote link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits 4.12:5 determine ...
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ICS1893AF Data Sheet - Release 8.6.6 Selector Field (Bits 4.4:0) When its Auto-Negotiation Sublayer is enabled, the ICS1893AF transmits its link capabilities to its remote Link Partner during the auto-negotiation process. The Selector Field is transmitted based on the value ...
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ICS1893AF Data Sheet - Release 8.7 Register 5: Auto-Negotiation Link Partner Ability Register Table 8-12 lists the bits for the Auto-Negotiation Link Partner Ability Register. An STA uses this register to determine the capabilities being advertised by the remote link ...
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ICS1893AF Data Sheet - Release 8.7.2 Acknowledge (bit 5.14) The ISO/IEC specification defines bit 5.14 as the Acknowledge bit. When this bit is a: • Zero, it indicates that the remote link partner has not received the ICS1893AF Link Control ...
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ICS1893AF Data Sheet - Release 8.8 Register 6: Auto-Negotiation Expansion Register Table 8-13 lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the Auto-Negotiation process. Note: For an explanation of acronyms used in Table 8-13. Auto-Negotiation ...
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ICS1893AF Data Sheet - Release 8.8.2 Parallel Detection Fault (bit 6.4) The ICS1893AF sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault occurs when the ICS1893AF cannot disseminate the technology being ...
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ICS1893AF Data Sheet - Release 8.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 8-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during ...
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ICS1893AF Data Sheet - Release 8.9.1 Next Page (bit 7.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next ...
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ICS1893AF Data Sheet - Release 8.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 8-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word ...
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ICS1893AF Data Sheet - Release 8.10.1 Next Page (bit 8.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next ...
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ICS1893AF Data Sheet - Release 8.11 Register 16: Extended Control Register Table 8-16 lists the bits for the Extended Control Register, which the ICS1893AF provides to allow an STA to customize the operations of the device. Note: 1. For an ...
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ICS1893AF Data Sheet - Release 8.11.1 Command Override Write Enable (bit 16.15) The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write (CW) bits located throughout the MII Register set. A two-step process ...
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ICS1893AF Data Sheet - Release 8.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893AF to transmit symbols that are typically classified as invalid. The purpose of this test bit ...
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ICS1893AF Data Sheet - Release 8.12 Register 17: Quick Poll Detailed Status Register Table 8-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed status of ...
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ICS1893AF Data Sheet - Release 8.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1893AF is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software ...
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ICS1893AF Data Sheet - Release 8.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11) The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the three Auto-Negotiation Monitor bits (bits 17.13:11). The Auto-Negotiation Progress Monitor continually examines the state of ...
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ICS1893AF Data Sheet - Release 8.12.5 100Base PLL Lock Error (bit 17.9) The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893AF has ever experienced a PLL Lock Error. A PLL Lock Error occurs when the ...
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ICS1893AF Data Sheet - Release 8.12.8 Halt Symbol (bit 17.6) The Halt Symbol bit indicates to an STA the detection of a Halt Symbol in a 100Base data stream by the ICS1893AF. During reception of a valid packet, the ICS1893AF ...
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ICS1893AF Data Sheet - Release 8.12.12 Jabber Detect (bit 17.2) Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has occurred. This bit is a 10Base-T function. 8.12.13 Remote Fault (bit 17.1) ...
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ICS1893AF Data Sheet - Release 8.13 Register 18: 10Base-T Operations Register The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893AF activity while the ICS1893AF is operating in 10Base-T mode. Note: 1. For an ...
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ICS1893AF Data Sheet - Release 8.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893AF has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the ...
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ICS1893AF Data Sheet - Release 8.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893AF from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, ...
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ICS1893AF Data Sheet - Release 8.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893AF operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to ...
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ICS1893AF Data Sheet - Release 8.14.1 Node/Repeater Configuration (bit 19.15) The Node/Repeater Configuration bit indicates the NOD/MODE. • In Node mode: – The SQE Test default setting is enabled. – The Carrier Sense signal (CRS) is asserted in response to ...
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ICS1893AF Data Sheet - Release Chapter 9 Pin Diagram, Listings, and Descriptions 9.1 ICS1893AF Pin Diagram POAC 1 VSS 2 P1CL 3 P2LI 4 VSS 5 P3TD 6 VDD 7 P4RD 8 10/100 9 TP_CT 10 VSS 11 TP_TXP 12 ...
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ICS1893AF Data Sheet - Release 9.2 ICS1893AF Pin Descriptions Table 9-1. MAC Interface Pins Signal Name MDIO MDC RXD3 RXD2 RXD1 RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS Table 9-2. Transformer Interface Pins Signal Name ...
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ICS1893AF Data Sheet - Release Table 9-4. Configuration Pins Signal Name 10/100 100TCSR 10TCSR REFIN RFOUT RESETn 9.2.1 Transformer Interface Pins The tables in this section list the ICS1893AF pins by their functional grouping. Table 9-5 lists the pins for ...
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ICS1893AF Data Sheet - Release 9.2.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins Table 9-6 lists the pins for the multi-function group of pins (that is, the multiplexed PHY Address / LED pins). Note: 1. During either a power-on ...
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ICS1893AF Data Sheet - Release Table 9-6. PHY Address and LED Pins Pin Pin Pin Name Number Type P1CL 3 Input or Output P2LI 4 Input or Output ICS1893AF, Rev D 10/26/04 Chapter 9 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893AF Data Sheet - Release Table 9-6. PHY Address and LED Pins Pin Pin Pin Name Number Type P3TD 6 Input or Output P4RD 8 Input or Output ICS1893AF, Rev. D 10/26/04 Chapter 9 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893AF Data Sheet - Release 9.2.3 Configuration Pins Table 9-7 lists the configuration pins. Table 9-7. Configuration Pins Pin Pin Name Number Type 10/100SEL 9 Output 10TCSR 15 Input 100TCSR 16 Input REF_IN 47 Input REF_OUT 46 Output RESETn 22 ...
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ICS1893AF Data Sheet - Release 9.2.4 MAC Interface Pins This section lists pin descriptions for each of the following interfaces • Section 9.2.4.1, “MAC Interface Pins for Media Independent Interface” 9.2.4.1 MAC Interface Pins for Media Independent Interface Table 9-8 ...
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ICS1893AF Data Sheet - Release Table 9-8. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type MDIO 26 Input/ Output RXCLK 34 Output ICS1893AF, Rev D 10/26/04 Chapter 9 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893AF Data Sheet - Release Table 9-8. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type RXD0, 31, Output RXD1, 30, RXD2, 29, RXD3 28 RXDV 32 Output RXER 35 Output TXCLK 37 Output ICS1893AF, ...
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ICS1893AF Data Sheet - Release Table 9-8. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type TXD0, 39, Input TXD1, 40, TXD2, 41, TXD3 42 TXEN 38 Input ICS1893AF, Rev D 10/26/04 Chapter 9 Pin ...
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ICS1893AF Data Sheet - Release 9.2.5 Ground and Power Pins Table 9-9. Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS ICS1893AF, Rev. D 10/26/04 Chapter 9 Pin ...
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ICS1893AF Data Sheet - Release Chapter 10 DC and AC Operating Conditions 10.1 Absolute Maximum Ratings Table 10-1 lists absolute maximum ratings. Stresses above these ratings can permanently damage the ICS1893AF. These ratings, which are standard values for ICS commercially ...
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ICS1893AF Data Sheet - Release 10.3 Recommended Component Values Table 10-3. Recommended Component Values for ICS1893AF Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std. 802.3 requirements that drive the tolerance ...
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ICS1893AF Data Sheet - Release 10.4 DC Operating Characteristics This section lists the ICS1893AF DC operating characteristics. 10.4.1 DC Operating Characteristics for Supply Current Table 10-4 lists the DC operating characteristics for the supply current to the ICS1893AF under various ...
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ICS1893AF Data Sheet - Release 10.4.3 DC Operating Characteristics for REF_IN Table 10-6 lists the 3.3-V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Table 10-6. 3.3-V DC Operating Characteristics for REF_IN ...
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ICS1893AF Data Sheet - Release 10.5 Timing Diagrams 10.5.1 Timing for Clock Reference In (REF_IN) Pin Table 10-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. ...
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ICS1893AF Data Sheet - Release 10.5.2 Timing for Transmit Clock (TXCLK) Pins Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 10-3 shows the timing diagram for the time ...
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ICS1893AF Data Sheet - Release 10.5.3 Timing for Receive Clock (RXCLK) Pins Table 10-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 10-4 shows the timing diagram for the time ...
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ICS1893AF Data Sheet - Release 10.5.4 100M MII: Synchronous Transmit Timing Table 10-11 lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK ...
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ICS1893AF Data Sheet - Release 10.5.5 10M MII: Synchronous Transmit Timing Table 10-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • ...
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ICS1893AF Data Sheet - Release 10.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing Table 10-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the ...
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ICS1893AF Data Sheet - Release 10.5.7 MII Management Interface Timing Table 10-14 lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). Table 10-14. MII Management Interface ...
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ICS1893AF Data Sheet - Release 10.5.8 10M Media Independent Interface: Receive Latency Table 10-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, ...
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ICS1893AF Data Sheet - Release 10.5.9 10M Media Independent Interface: Transmit Latency Table 10-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • ...
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ICS1893AF Data Sheet - Release 10.5.10 100M / MII Media Independent Interface: Transmit Latency Table 10-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the ...
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ICS1893AF Data Sheet - Release 10.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: ...
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ICS1893AF Data Sheet - Release 10.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-19 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: ...
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ICS1893AF Data Sheet - Release 10.5.13 100M MII Media Independent Interface: Receive Latency Table 10-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the ...
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ICS1893AF Data Sheet - Release 10.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion Table 10-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that ...
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ICS1893AF Data Sheet - Release 10.5.15 Reset: Power-On Reset Table 10-22 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 10-16 shows the ...
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... Table 10-23. Hardware Reset and Power-Down Timing Time Period t1 RESETn Active to Device Isolation and Initialization t2 Minimum RESETn Pulse Width t3 RESETn Released to TXCLK Valid Figure 10-17. Hardware Reset and Power-Down Timing Diagram REF_IN RESETn TXCLK Valid ...
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ICS1893AF Data Sheet - Release 10.5.17 10Base-T: Heartbeat Timing (SQE) Table 10-24 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: • ...
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ICS1893AF Data Sheet - Release 10.5.18 10Base-T: Jabber Timing Table 10-25 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and ...
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... Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 10-26. 10Base-T Normal Link Pulse Timing Time Period t1 Normal Link Pulse Width t2 Normal Link Pulse to Normal Link Pulse Period Figure 10-20. 10Base-T Normal Link Pulse Timing Diagram TP_TXP ICS1893AF, Rev D 10/26/04 Figure 10-20 shows the timing diagram for the time periods ...
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... Period t1 Clock/Data Pulse Width t2 Clock Pulse-to-Data Pulse Timing t3 Clock Pulse-to-Clock Pulse Timing t4 Fast Link Pulse Burst Width t5 Fast Link Pulse Burst to Fast Link Pulse Burst t6 Number of Clock/Data Pulses in a Burst Figure 10-21. Auto-Negotiation Fast Link Pulse Timing Diagram Clock Pulse ...
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ICS1893AF Data Sheet - Release Chapter 11 Physical Dimensions of ICS1893AF Package Figure 11-1. ICS1893AF Physical Dimensions INDEX INDEX AREA AREA SYMBOL α VARIATIONS ...
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... ICS1893AF Data Sheet - Release Chapter 12 Ordering Information Figure 12-1. shows ordering information for the ICS1893AF. "T" = Tape and Reel. Part / Order Number ICS1893AFLFT ICS1893AFILFT ICS1893AFLF ICS1893AFILF ICS1893AF, Rev. D 10/26/04 Marking Package 1893AFLF 48-Lead 300-mil SSOP 1893AFILF 48-Lead 300-mil SSOP 1893AFLF 48-Lead 300-mil SSOP ...
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ICS1893AF Data Sheet - Release Integrated Circuit Systems, Inc. Corporate Headquarters: San Jose, CA Operations: Web Site: ICS1893AF, Rev D 10/26/04 2435 Boulevard of the Generals Norristown, PA 19403 Telephone: 610-630-5300 Fax: 610-630-5399 525 Race Street San Jose, CA 95126-3448 ...