AT25DQ321-SH-B Adesto Technologies, AT25DQ321-SH-B Datasheet - Page 11

• Manufacturer Part Number: AT25DQ321-SH-B
• Description: Flash 32M 2.7-3.6V, 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DQ321-SH-B

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 19 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Factory Pack Quantity: 95

7.2
Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has
been specified. Unlike the standard Read Array command however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by f
perform the Dual-Output Read Array operation, the CS pin must first be asserted and the opcode of 3Bh must be clocked
into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting
address location of the first byte to read within the memory array. Following the three address bytes, a single dummy
byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the I/O
output on the I/O
same data byte will be output on the I/O
on the I/O
cycles. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading back at the
beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the
beginning of the array.
Deasserting the CS pin will terminate the read operation and put the I/O
can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-4. Dual-Output Read Array
SO (I/O
SI (I/O
SCK
CS
0
1
)
)
1
and I/O
1
pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O
0
pins, respectively. The sequence continues with each byte of data being output after every four clock
MSB
High-impedance
1
0
0
and I/O
0
1
1
2
Opcode
1
3
0
pins. The data is always output with the MSB of a byte first, and the MSB is always
1
4
0
5
1
6
0
1
7
pin. During the next clock cycle, bits 5 and 4 of the first data byte will be output
MSB
A
8
A
9
A
Address Bits A23-A0
10 11
A
A
12
A
A
29 30
A
A
31 32
MSB
X
1-0
X
33
pins into a high-impedance state. The CS pin
X
34
Don't Care
X
35
X
36
AT25DQ321 [DATASHEET]
X
37 38
X
X
39
MSB
D
D
40
Data Byte 1
6
7
Output
D
D
41
8718D–DFLASH–12/2012
4
5
D
D
42 43
2
3
1
D
D
pin while bit 6 of the
0
1
D
D
44
Data Byte 2
6
7
Output
D
D
45
4
5
D
D
46
2
3
RDDO
D
D
47 48
0
1
MSB
D
D
6
7
. To
D
D
4
5
11