AT25DL081-SSHN-T Adesto Technologies, AT25DL081-SSHN-T Datasheet - Page 39

• Manufacturer Part Number: AT25DL081-SSHN-T
• Description: Flash 8M 1.65-1.95V 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DL081-SSHN-T

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 8 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 1.95 V
• Supply Voltage - Min: 1.65 V
• Maximum Operating Current: 20 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8

11.2
Write Status Register Byte 1
The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Register and/or to perform a
Global Protect or Global Unprotect operation. Before the Write Status Register Byte 1 command can be issued, the Write
Enable command must have been previously issued to set the WEL bit in the Status Register to a Logical 1.
To issue the Write Status Register Byte 1 command, the CS pin must first be asserted and then the opcode 01h must be
clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a don’t-care bit,
four data bits to denote whether a Global Protect or Unprotect should be performed, and two additional don’t-care bits
(see
the SPRL bit in the Status Register will be modified, and the WEL bit in the Status Register will be reset back to a Logical
0. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before the Write Status Register Byte 1 command was
executed (the prior state of the SPRL bit) will determine whether or not a Global Protect or Global Unprotect will be
performed. Please refer to
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of
the SPRL bit will not change, no potential Global Protect or Unprotect will be performed, and the WEL bit in the Status
Register will be reset back to the Logical 0 state.
If the WP pin is asserted, then the SPRL bit can only be set to a Logical 1. If an attempt is made to reset the SPRL bit to
a Logical 0 while the WP pin is asserted, then the Write Status Register Byte 1 command will be ignored and the WEL bit
in the Status Register will be reset back to the Logical 0 state. In order to reset the SPRL bit to a Logical 0, the WP pin
must be deasserted.
Table 11-3. Write Status Register Byte 1 Format
Figure 11-2. Write Status Register Byte 1
SCK
SO
CS
SI
SPRL
Table
Bit 7
11-3). Any additional data bytes that are sent to the device will be ignored. When the CS pin is deasserted,
MSB
High-impedance
0
0
Bit 6
0
1
X
0
2
Opcode
0
3
“Global Protect/Unprotect” on page 25
0
4
0
5
0
6
Bit 5
1
7
MSB
D
8
X
9
Status Register In
D
10 11
Byte 1
D
Global Protect/Unprotect
Bit 4
D
12
D
13
X
14 15
X
Bit 3
for more details.
Bit 2
AT25DL081 [DATASHEET]
Bit 1
8732E–DFLASH–1/2013
X
Bit 0
X
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