SST39SF512-90-4C-WH Microchip Technology, SST39SF512-90-4C-WH Datasheet
SST39SF512-90-4C-WH
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SST39SF512-90-4C-WH Summary of contents
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... SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF512 devices write (Program or Erase) with a 4.5-5.5V power supply. The SST39SF512 device conforms to JEDEC standard pinouts for x8 memories. Featuring ...
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... CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39SF512 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. ...
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... Kbit Multi-Purpose Flash SST39SF512 Data# Polling ( When the SST39SF512 are in the internal Program opera- tion, any attempt to read DQ will produce the complement 7 of the true data. Once the Program operation is completed, DQ will produce true data. Note that even thought DQ ...
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... 32-lead PLCC Top View DQ0 32- PLCC LEAD 4 512 Kbit Multi-Purpose Flash SST39SF512 SuperFlash Memory Y-Decoder 1149 B1.1 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 1149 F02b.6 S71149-05-000 11/03 ...
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... Kbit Multi-Purpose Flash SST39SF512 A11 A9 A8 A13 A14 NC WE A15 A12 FIGURE SSIGNMENTS FOR FIGURE SSIGNMENTS FOR ©2003 Silicon Storage Technology, Inc Standard Pinout 6 7 Top View 8 9 Die Up 10 ...
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... Write Enable To control the Write operations. V Power Supply To provide 4.5-5.5V supply DD V Ground Connection Unconnected pins Most significant address for SST39SF512 and TABLE PERATION ODES ELECTION Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode 1 ...
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... SST Manufacturer’ BFH, is read with SST39SF512 Device ID = B4H, is read with A 6. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied ...
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... V 2.0 V 0 OWER UP IMINGS Minimum Specification 10,000 100 100 + 512 Kbit Multi-Purpose Flash SST39SF512 Test Conditions Address input f=1/T ILT IHT Max DD DD CE#=V , OE#=WE#=V , all I/Os open IL IH CE#=WE#=V , OE#= CE#= Max CE#=V -0.3V Max ...
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... SE T Chip-Erase SCE 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc 4.5-5.5V ARAMETERS IMING ARAMETERS 9 Data Sheet SST39SF512-70 Min Max Units ...
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... Data Sheet ADDRESS A MS-0 CE# OE WE# HIGH-Z DQ 7-0 Note Most significant address for SST39SF512 FIGURE EAD YCLE IMING 5555 ADDRESS OE# CE# DQ 7-0 AA SW0 Note Most significant address for SST39SF512 FIGURE 5: WE# C ONTROLLED © ...
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... Note Most significant address for SST39SF512 FIGURE 6: CE# C ONTROLLED ADDRESS A MS-0 CE# OE# WE Note Most significant address for SST39SF512 FIGURE ATA OLLING IMING ©2003 Silicon Storage Technology, Inc. INTERNAL PROGRAM OPERATION STARTS 2AAA ...
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... Data Sheet ADDRESS A MS-0 CE# OE# WE Note: Toggle bit output is always high first Most significant address for SST39SF512 FIGURE OGGLE IT IMING 5555 ADDRESS A MS-0 CE# OE WE# DQ 7-0 AA SW0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met ...
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... AA SW0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10 Sector Address Most significant address for SST39SF512 FIGURE 10: WE# C ONTROLLED Three-byte sequence for ADDRESS A 14-0 5555 2AAA ...
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... THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 ADDRESS A 14-0 DQ 7-0 AA CE# OE WE# SW0 FIGURE 12 OFTWARE XIT AND ©2003 Silicon Storage Technology, Inc. 2AAA 5555 IDA T WHP SW1 SW2 R ESET 14 512 Kbit Multi-Purpose Flash SST39SF512 1149 F10.0 S71149-05-000 11/03 ...
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... Kbit Multi-Purpose Flash SST39SF512 V IHT INPUT V ILT AC test inputs are driven at V (2.4V) for a logic “1” and V IHT inputs and outputs are V (2.0 V) and V HT FIGURE 13 NPUT UTPUT TO DUT FIGURE 14 EST OAD XAMPLE ©2003 Silicon Storage Technology, Inc. ...
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... Kbit Multi-Purpose Flash Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Byte Address/Byte Data Wait for end of Program (TBP' Data# Polling bit or Toggle bit operation) Program Completed 1149 F13.1 16 SST39SF512 S71149-05-000 11/03 ...
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... Kbit Multi-Purpose Flash SST39SF512 Internal Timer Program/Erase Initiated Wait SCE Program/Erase Completed FIGURE 16 AIT PTIONS ©2003 Silicon Storage Technology, Inc. Toggle Bit Byte-Program/ Sector Erase Initiated Read byte Read same No byte No Does DQ 6 match? Yes Write Completed ...
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... Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: F0H Address: 5555H Wait T IDA Return to normal operation C F OMMAND LOWCHARTS 18 512 Kbit Multi-Purpose Flash SST39SF512 Load data: F0H Address: XXH Wait T IDA Return to normal operation 1149 F15.1 S71149-05-000 11/03 ...
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... Kbit Multi-Purpose Flash SST39SF512 Chip-Erase Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Wait T SCE Chip-Erase ...
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... PRODUCT ORDERING INFORMATION SST 39 SF 512 - XXXX - XXX Valid combinations for SST39SF512 SST39SF512-70-4C-NH SST39SF512-70-4C-WH SST39SF512-70-4C-NHE SST39SF512-70-4C-WHE SST39SF512-70-4I-NH SST39SF512-70-4I-WH SST39SF512-70-4I-NHE SST39SF512-70-4I-WHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © ...
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... Kbit Multi-Purpose Flash SST39SF512 PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 Optional .447 Pin #1 .048 Identifier .042 .042 .048 .595 .553 .585 .547 .050 BSC Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). ...
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... Silicon Storage Technology, Inc. 1.655 1.645 .200 .170 .150 .120 .100 BSC .022 .016 (PDIP) Description www.SuperFlash.com or www.sst.com 22 512 Kbit Multi-Purpose Flash SST39SF512 .625 .600 .550 .530 7˚ 4 PLCS. .012 .008 .600 BSC 32-pdip-PH-3 Date Apr 2002 Mar 2003 Nov 2003 S71149-05-000 0˚ ...