92HD90B0X5NLGXYAX8 IDT, 92HD90B0X5NLGXYAX8 Datasheet - Page 279

• Manufacturer Part Number: 92HD90B0X5NLGXYAX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of 92HD90B0X5NLGXYAX8

• Rohs: yes
• Part # Aliases: IDT92HD90B0X5NLGXYAX8

92HD98
SINGLE CHIP PC AUDIO SYSTEM, CODEC+MONO SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
verb F71/771 (Left)
verb F72/772 (Right)
verb 773 (Left and Right -
write only)
verb F76/776
Register Address
Register Address
7.29.1.1. SPKVOL L/R Registers
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions.
7.29.1.2. AIC1 Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions
7:0
7
6
5
4
3:2
1:0
Bit
Bit
VOL[7:0]
SCLKINV
MS
LRSWAP
LRP
WL[1:0]
FORMAT[1:0]
Label
Label
RW
RW
RW
RW
RW
RW
RW
Type
Type
30
0
1
0
0
10
10
Default
Default
279
+36 to -91.5dB in 0.75dB steps
0x00 = +36dB
0x01 = +35.25dB
...
0x2F = +0.75dB
0x30 = 0dB
0x31 = -0.75dB
...
0xA9 = -90.75
0xAA to 0xFE = -91.5dB
0xFF = mute
0 =SCLK not inverted (data and LRCLK transition on falling
edge of SCLK)
1 = invert SCLK (data and LRCLK transition on rising edge of
SCLK)
Master/Slave
0 = SCLK and LRCLK are inputs (slave mode)
1 = SCLK and LRCLK are outputs (master mode)
Swap Left and Right Samples
0 = Left sample first in frame
1 = Right sample first in frame
Left/Right (I2S_LRCLK) Polarity
0 = default per format
1 = LRCLK inverted
Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = Reserved
link format
00 = Right Justified
01 = Left Justified
10 = I2S
11 = reserved
Description
Description
V 1.2 3/12
92HD98