MC10ELT22DG ON Semiconductor, MC10ELT22DG Datasheet

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MC10ELT22DG

Manufacturer Part Number
MC10ELT22DG
Description
IC XLATOR DUAL TTL-PECL DF 8SOIC
Manufacturer
ON Semiconductor
Series
10ELTr
Datasheet

Specifications of MC10ELT22DG

Logic Function
Translator
Number Of Bits
2
Input Type
TTL
Output Type
PECL
Number Of Channels
2
Number Of Outputs/channel
1
Differential - Input:output
No/Yes
Propagation Delay (max)
1.1ns
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Supply Voltage
4.75 V ~ 5.25 V
Logic Type
Translator
Logic Family
ECL
Translation
TTL to PECL
High Level Output Current
- 50 mA
Low Level Output Current
50 mA
Propagation Delay Time
1.5 ns @ 4.75 V to 5.25 V
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
MC10ELT22DGOS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC10ELT22DG
Manufacturer:
ON Semiconductor
Quantity:
76
Part Number:
MC10ELT22DG
Manufacturer:
ON/安森美
Quantity:
20 000
MC10ELT22, MC100ELT22
5.0 V Dual TTL to Differential
PECL Translator
translator. Because PECL (Positive ECL) levels are used only +5 V
and ground are required. The small outline 8-lead package and the low
skew, dual gate design of the ELT22 makes it ideal for applications
which require the translation of a clock and a data signal.
Features
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 9
The MC10ELT/100ELT22 is a dual TTL to differential PECL
1.2 ns Typical Propagation Delay
< 300 ps Typical Output to Output Skew
PNP TTL Inputs for Minimal Loading
Flow Through Pinouts
Operating Range: V
No Internal Input Pulldown Resistors
Pb−Free Packages are Available
CC
= 4.75 V to 5.25 V with GND = 0 V
1
*For additional information, see Application Note
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
AND8002/D.
CASE 948R
DT SUFFIX
8
CASE 751
D SUFFIX
TSSOP−8
(Note: Microdot may be in either location)
8
SO−8
ORDERING INFORMATION
1
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
http://onsemi.com
8
1
8
1
Publication Order Number:
HLT22
ALYW
ALYWG
HT22
DIAGRAMS*
G
G
MARKING
MC10ELT22/D
8
1
8
1
KLT22
ALYW
ALYWG
KT22
G
G

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MC10ELT22DG Summary of contents

Page 1

MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and ...

Page 2

PECL TTL Figure 1. Logic Diagram and Pinout Assignment Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply CC V Input Voltage IN I Output Current out T Operating Temperature Range A T Storage Temperature Range stg Thermal Resistance (Junction−to−Ambient Thermal Resistance (Junction−to−Case ...

Page 4

Table 6. TTL INPUT DC CHARACTERISTICS Symbol Characteristic I Input HIGH Current IH I Input HIGH Current IHH I Input LOW Current IL V Input Clamp Diode Voltage IK V Input HIGH Voltage IH V Input LOW Voltage IL NOTE: ...

Page 5

... Q Driver Device Q Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC10ELT22D MC10ELT22DG MC10ELT22DR2 MC10ELT22DR2G MC10ELT22DT MC10ELT22DTG MC10ELT22DTR2 MC10ELT22DTR2G MC100ELT22D MC100ELT22DG MC100ELT22DR2 MC100ELT22DR2G MC100ELT22DT MC100ELT22DTG MC100ELT22DTR2 MC100ELT22DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D ...

Page 6

Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

Page 7

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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