MAX9273GTL+ Maxim Integrated, MAX9273GTL+ Datasheet - Page 27

• Manufacturer Part Number: MAX9273GTL+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 22-bit Coax/STP serializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9273GTL+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CMOS/LVCMOS
• Output Type: CML
• Number Of Inputs: 22
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-40 EP
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

In I
face sends and receives data through an I
2-wire interface. The interface uses a serial-data line
(SDA) and a serial-clock line (SCL) to achieve bidirec-
tional communication between master and slave(s). A FC
master initiates all data transfers to and from the device
and generates the SCL clock that synchronizes the data
transfer. When an I
device’s control-channel port, the remote-side device’s
control-channel port becomes an I
faces with remote-side I
must accept clock stretching that is imposed by the seri-
alizer (holding SCL low). The SDA and SCL lines operate
as both an input and an open-drain output. Pullup resis-
tors are required on SDA and SCL. Each transmission
consists of a START condition
ter, followed by the device’s 7-bit slave address plus a
R/W bit, a register address byte, one or more data bytes,
and finally a STOP condition.
Maxim Integrated
Figure 23. Format Conversion Between GMSL UART and I
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
2
C-to-I
FC
FC
SYNC FRAME
SYNC FRAME
UART-TO-I
2
UART-TO-I
C mode, the serializer control-channel inter-
11
11
2
2
C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
C CONVERSION OF READ PACKET (I2CMETHOD = 1)
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
2
C transaction starts on the local-side
DEVICE ID + RD
DEVICE ID + WR
2
C peripherals. The I
11
11
PERIPHERAL
PERIPHERAL
: MASTER TO SLAVE
(Figure
S
1
REGISTER ADDRESS
REGISTER ADDRESS
2
22-Bit GMSL Serializer with Coax or
C master that inter-
DEV ID
7
6) sent by a mas-
11
11
I
2
2
C Interface
W A
C-compatible
1
1
2
: SLAVE TO MASTER
C master
NUMBER OF BYTES
NUMBER OF BYTES
2
C with Register Address (I2CMETHOD = 1)
11
11
1
S
S: START
DEV ID
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high
finished communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission.
One data bit is transferred during each clock pulse
(Figure
SCL is high.
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data
Thus, each byte transferred effectively requires nine bits.
The master generates the 9th clock pulse, and the recipi-
ent pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
7
DATA 0
1 1
R A
11
25). The data on SDA must remain stable while
P: STOP
ACK FRAME
DATA 0
11
8
A: ACKNOWLEDGE
DATA 0
8
1
A
STP Cable Drive
DATA N
1
A
(Figure
11
START and STOP Conditions
DATA 0
11
DATA N
8
24). When the master has
DATA N
MAX9273
A P
1 1
8
ACK FRAME
11
1 1
A P
Acknowledge
DATA N
Bit Transfer
11
(Figure
26).
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