AT91SAM9261S-CU Atmel, AT91SAM9261S-CU Datasheet - Page 33

• Manufacturer Part Number: AT91SAM9261S-CU
• Description: ARM Microcontrollers - MCU BGA IND TEMP
• Manufacturer: Atmel
• Series: 91Sr

Specifications of AT91SAM9261S-CU

• Product Category: ARM Microcontrollers - MCU
• Rohs: yes
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 190 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 16 KB
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: BGA-217
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USB
• Length: 15 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Program Memory Type: ROM
• Factory Pack Quantity: 126
• Supply Voltage - Max: 1.32 V, 3.6 V
• Supply Voltage - Min: 1.08 V, 1.65 V, 2.7 V, 3 V

10.7
10.8
10.9
6242ES–ATARM–11-Sep-09
Serial Peripheral Interface
Two-wire Interface
USART
• Supports communication with serial external devices
• Master or slave serial peripheral bus interface
• Very fast transfers supported
• Compatibility with standard two-wire serial memory
• One, two or three bytes for slave address
• Sequential read/write operations
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
• IrDA modulation and demodulation
– Four chip selects with external decoder support allow communication with up to
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
– External co-processors
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
– Programmable delay between consecutive transfers
– Selectable mode fault detection
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By-8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
– NACK handling, error counter with repetition and iteration limit
fifteen peripherals
Sensors
and data per chip select
AT91SAM9261S
33