MAX9242EUM-TD Maxim Integrated, MAX9242EUM-TD Datasheet - Page 18

• Manufacturer Part Number: MAX9242EUM-TD
• Description: Serializers & Deserializers - Serdes
• Manufacturer: Maxim Integrated

21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 20) is:
The MAX9242/MAX9244/MAX9246/MAX9254 have fail-
safe LVDS inputs in non-DC-balanced mode (Figure 1).
Fail-safe drives the outputs low when the corresponding
LVDS input is open, undriven and shorted, or undriven
and parallel terminated. The fail-safe on the LVDS clock
input drives all outputs low when power is stable. Fail-
safe does not operate in DC-balanced mode.
In DC-balanced mode, the inverting and noninverting
LVDS inputs are internally connected to +1.2V through
42kΩ (min) to provide biasing for AC-coupling (Figure 1).
To prevent switching due to noise when the clock input
is not driven, bias the clock inputs (RxCLKIN+,
Figure 19. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
18
C = -(4 x t
PWRDWN
TxCLK IN
______________________________________________________________________________________
TxIN
Input Bias and Frequency Detection
7
7
7
B
x DSV) / (ln (1 - D) x (R
(7 + 2):1
(7 + 2):1
(7 + 2):1
PLL
MAX9209/MAX9213
21:3 SERIALIZER
T
+ R
R
O
O
SERIALIZER INSTEAD OF THE DESERIALIZER.
Fail-Safe
)) (Eq 3)
TxOUT
TxCLK OUT
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
HIGH-FREQUENCY, CERAMIC
RxCLKIN-) to differential +15mV by connecting a 10kΩ
±1% pullup resistor between the noninverting input and
LVDSV
the inverting input and ground. These bias resistors,
along with the 100Ω ±1% tolerant termination resistor,
provide +15mV of differential input. The +15mV bias
causes some small degradation of RSKM proportional to
the slew rate of the clock input. For example, if the clock
transitions 250mV in 500ps, the slew rate of 0.5mV/ps
reduces RSKM by 30ps.
In non-DC-balanced mode, leave unused LVDS data
inputs open. In non-DC-balanced mode, the input fail-
safe circuit drives the corresponding outputs low, and no
pullup or pulldown resistors are needed. In DC-balanced
mode, at each unused LVDS data input, pull the inverting
input up to LVDSV
noninverting input down to ground using a 10kΩ resistor.
Do not connect a termination resistor. The pullup and
pulldown resistors drive the corresponding outputs low
and prevent switching due to noise.
100Ω
100Ω
100Ω
100Ω
RxCLK IN
R
RxIN__
T
CC
, and a 10kΩ ±1% pulldown resistor between
MAX9242/MAX9244/MAX9246/MAX9254
CC
3:21 DESERIALIZER
using a 10kΩ resistor, and pull the
Unused LVDS Data Inputs
1:(9 - 2)
1:(9 - 2)
1:(9 - 2)
+ FIFO
+ FIFO
+ FIFO
PLL1 +
SSPLL
7
7
7
RxOUT_
PWRDWN
RxCLK OUT